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Advance Information
This document contains information on a product under development. The parametric information contains target parameters that are subject to change.
CN8380
Quad T1/E1 Line Interface
The CN8380 is a fully integrated quad line interface unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It is designed to complement T1/E1 framers or operate as a stand-alone line interface to synchronous or plesiochronous mappers and multiplexers. The device can be controlled through a host mode serial port or by hardware mode operation, where device control and status are obtained through non-multiplexed dedicated pins. Many of these pins are also dedicated to individual channels for maximum flexibility and for use in redundant systems. Integrated in the CN8380 device is a clock rate adapter (CLAD), which provides various low-jitter programmable system clock outputs. The receive section of the CN8380 is designed to recover encoded signals from lines having up to 12 dB of attenuation. The transmit section consists of a programmable, precision pulse shaper.
Distinguishing Features
* Four T1/E1 short haul line interfaces in a single chip * On-chip CLAD /system synchronizer * Digital (crystal-less) jitter attenuators selectable for transmitter/receiver on each line interface * Meets AT&T pub 62411 jitter specs * Meets ITU G.703, ETS 300 011 (PSTNX) Connections * AMI/B8ZS/HDB3 line codes * Host serial port or hardware only control modes * On-chip receive clock recovery * Common transformers for 120/75 E1 and 100 T1 * Low-power 3.3 V power supply * Transmitter performance monitor * Compatible with latest ANSI, ITU-T, and ETSI standards * 128-pin MQFP package * Remote and local loopbacks
Functional Block Diagram
Local Analog Loopback
RRING[1]
Remote Line Loopback
Local Digital Loopback
RTIP[1]
Receiver
Clock and Data Recovery
RLOS Detect
ZCS Decode
RPOSO[1] RNEGO[1] RCKO[1]
Applications
* SONET/SDH multiplexers * T3 and E3/E4 (PDH) multiplexers * ATM multiplexers * Voice compression and voice processing equipment * WAN routers and bridges * Digital loop carrier terminals (DLC) * HDSL terminal units * Remote concentrators * Central office equipment * PBXs and rural switches * PCM/voice channel banks * Digital access and cross-connect systems (DACS)
Jitter Attenuator
XTIP[1] XRING[1]
Driver
Pulse Shaping
TAIS
ZCS Decode
TPOSI[1] TNEGI[1] TCLK[1] LIU #1 LIU #2 LIU #3 LIU #4
JTAG Test Port 5 JTAG Test Signals 8380_001
Control 47 4
Clock Rate Adapter
Control and Host 10 MHz Variable 1.544 Alarm Signals Serial Fixed Reference MHz Port Reference
2.048 32.768 8 kHz-32 MHz MHz MHz Selectable
Data Sheet
Advance Information
N8380DSA April 26, 1999
Ordering Information
Model Number CN8380EPF CN8398EVM Package 128-pin MQFP BT00-D660-001 Operating Temperature -40 C to +85 C
Revision History
Revision A Level Advance Date April 26, 1999 Description Created
Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant and "What's Next in Communications Technologies" are trademarks of Conexant Systems, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. (c) 1999 Conexant Systems, Inc. Printed in U.S.A. All Rights Reserved
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N8380DSA
Conexant
Advance Information
CN8398EVM Octal T1/E1 Evaluation Module
Eight RJ48C T1 or E1 Line Connections
CN8380 Quad T1/E1 LIU
CN8380 Quad T1/E1 LIU
Microprocessor Control
CN8398 Octal T1/E1 Framer
Local PCM Highway (i.e., 2 @ 8192 kbps)
8380_002
Contact a Conexant representative for EVM availability and price.
Detailed Feature Summary
Interface Compatibility * * * T1.102-1993 G.703 at 1.544 or 2.048 Mbps ITU-T Recommendation I.431 Line Codes * Bipolar alternate mark inversion line coding * Optional zero code suppression: - Independent transmit and receive - T1: B8ZS - E1: HDB3 Loopbacks * Remote loopback towards line - With or without JAT - Retains BPV transparency Local loopback towards system - Analog line loopback - Local digital loopback Simultaneous local and remote line loopbacks * Programmable input timing reference: - Receive recovered clock from any channel - Internal clock (REFCKI) - CLADI Subrate CLADI timing reference: - Line rate /2N, N = 0 to 7 - References as low as 8 kHz
Receive Line Interface * * * External Termination Equalizer compensation for - 20 dB bridged monitor levels + 3 dB to -12 dB receiver sensitivity
*
Host Serial Interface * * * Compatible with existing framers Compatible with microprocessor serial ports Bit rates up to 8 Mbps
Transmit Line Interface Pulse shapes for 0-655 ft., in 133 ft. steps (T1 DSX-1) * External termination for improved return loss * Line driver enable/disable for protection switching * Output short circuit protection (for BABT applications) Jitter Attenuator Elastic Store * * * Receive or transmit direction 8-, 16-, 32-, 64-, or 128-bit depth Automatic and manual centering * * *
*
In-Service Performance Monitoring * Transmit alarm detectors: - Loss of Transmit Clock (TLOC) - Transmit Short Circuit (TSHORT) Receive alarm detectors: - Loss of Signal (RLOS) - Loss of Analog Input (RALOS) - Bipolar/Line Code Violations Automatic and on-demand transmit alarms: - AIS following TLOC - Automatic AIS clock switching
Clock Rate Adapter * Outputs jitter attenuated line rate clock - CLK1544 = 1544 k (T1) - CLK2048 = 2048 k (E1) CLAD output supports 14 output clock frequencies: 8 kHz to 32,768 kHz *
*
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Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x i 1.0 2.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 2.2.2 2.2.3 2.2.4 Hardware Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.2 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 2-3 2-3 2-4 2-5 2-5 2-5
2.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.1 Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.1.1 Raw Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.1.2 Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.1.3 Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.1.4 Loss Of Signal Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.2.1 Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.2.2 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Receive Jitter Attenuator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 RZCS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Receive Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.5.1 Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.5.2 Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.2
2.3.3 2.3.4 2.3.5
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CN8380
Quad T1/E1 Line Interface
2.4
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.1 Transmit Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.1.1 Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.1.2 Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 TZCS Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Transmit Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 All 1s AIS Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4.6.1 Transmit Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4.6.2 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Transmitter Output Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.7.1 Short Circuit Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.7.2 Driver Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Local Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Local Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Remote Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.4.2 2.4.3 2.4.4 2.4.5 2.4.6
2.4.7
2.5
Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.5.1 2.5.2 2.5.3
2.6 2.7
Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Clock Rate Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.7.1 2.7.2 2.7.3 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Device Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.8
Test Access Port (JTAG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.8.1 2.8.2
3.0
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 3.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Global Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 00--Device Identification (DID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 01--Global Configuration (GCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 02--CLAD Configuration (CLAD_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 03--CLAD Frequency Select (CSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 04--CLAD Phase Detector Scale Factor (CPHASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 05--CLAD Test (CTEST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 06--CLAD Status (CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 07--(FREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 08--(TESTA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 09--(TESTA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 0A--(FUSE_CH1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 0B--(FUSE_CH2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 0C--(FUSE_CH3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 0D--(FUSE_CH4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 0E--(FUSE_RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 0F--(TESTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
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Quad T1/E1 Line Interface 3.3
Table of Contents
Per Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 10, 20, 30, 40--Jitter Attenuator Configuration (JAT_CR) . . . . . . . . . . . . . . . . . . . . . . . 3-10 11, 21, 31, 41--Receiver Configuration (RLIU_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 12, 22, 32, 42 --Transmitter Configuration (TLIU_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 13, 23, 33, 43--LIU Control (LIU_CTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 15, 25, 35, 45--Alarm Status (ALARM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 16, 26, 36, 46--Interrupt Status Register (ISR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 17, 27, 37, 47--Interrupt Enable Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4
Transmitter Shape Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 18 - 1F--Transmit PULSE Shape CONFIGURATION (SHAPE1) . . . . . . . . . . . . . . . . . . . . 3-17 28 - 2F--Transmit PULSE Shape CONFIGURATION (SHAPE2) . . . . . . . . . . . . . . . . . . . . 3-17 38 - 3F--Transmit PULSE Shape CONFIGURATION (SHAPE3) . . . . . . . . . . . . . . . . . . . . 3-17 48 - 4F--Transmit PULSE Shape CONFIGURATION (SHAPE4) . . . . . . . . . . . . . . . . . . . . 3-17 50--(TESTA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 51--(TESTA4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
4.0
Electrical/Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 4.2 4.3 4.4 4.5 4.6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Appendix A: Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B: External Component Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Appendix C: Acronym List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
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Quad T1/E1 Line Interface
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List of Figures
List of Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure B-1. CN8380 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 CN8380 Logic Diagram (Host Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 CN8380 Logic Diagram (Hardware Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Host Serial Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Raw Mode Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Transmit Pulse Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Transmit Termination Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Receiver Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Typical JAT Transfer Characteristics with Various JAT Sizes . . . . . . . . . . . . . . . . . . . . . . 2-24 CLAD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 XOE Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CLAD Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Receiver Signals Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Transmitter Signals Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Host Serial Port Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Host Serial Port Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Host Serial Port Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 128-Pin MQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Minimum Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
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List of Figures
CN8380
Quad T1/E1 Line Interface
x
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N8380DSA
CN8380
Quad T1/E1 Line Interface
List of Tables
List of Tables
Table 1-1. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 3-1. Table 3-2. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table A-1. Table B-1. Table B-2. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Line Compatible Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Transmitter Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Transmit Pulse Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Transmit Termination Option A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Transmit Termination Option B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Transmit Termination Option C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Transmit Termination Option D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Transmit Termination Option E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Loopback Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 CLAD Outputs and Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 CLAD Reference Frequencies and Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Sample Alternate Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Transmitter Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 XOE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 RESET Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CLAD Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Receiver Signals Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Transmitter Signals Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Host Serial Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 JTAG Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Applicable Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Transformer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 REFCKI (10 MHz) Crystal Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
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List of Tables
CN8380
Quad T1/E1 Line Interface
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N8380DSA
1
1.0 Pin Descriptions
The CN8380 is packaged in a 128-pin metric quad flat pack (MQFP). A pinout diagram is illustrated in Figure 1-1. Logic diagrams are illustrated in Figure 1-2 and Figure 1-3. Pin labels and numbers, input/output functions, and descriptions are provided in Table 1-1. The following input pins contain an internal pull-up resistor (> 50 k) and may remain unconnected if unused or if the active high input state is desired: XOE [1:4] TAIS [1:4] RAWMD [1:4] RLOOP [1:4] LLOOP [1:4] HM UNIPOLAR JDIR/SCLK JSEL(2)/SDI JSEL(1)/CS JSEL(0) RESET HTERM CLK_POL PTS(2:0) TDI (Unused if JTAG not connected) TMS (Disables JTAG if not connected) TCK (Unused if JTAG not connected) TRST (Unused if JTAG not connected)
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1-1
1.0 Pin Descriptions
CN8380
Quad T1/E1 Line Interface
Figure 1-1. CN8380 Pinout Diagram
TACKI EACKI RLOOP [4] RLOOP [3] RLOOP [2] RLOOP [1] LLOOP [4] LLOOP [3] LLOOP [2] LLOOP [1] TAIS [4] TAIS [3] TAIS [2] TAIS [1] UNIPOLAR VDD VSS RLOS [4] RLOS [3] RLOS [2] RLOS [1] VGG TCK TMS TDI TDO 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 CLADI VAACL GNDCL REFCKI VSS VDD CLK32 CLK1544 CLK2048 CLADO VSS VDD RNEGO/BPV [4] RPOSO/RDATO [4] RCKO [4] TNEGI [4] TPOSI/TDATI [4] TCLK [4] RNEGO/BPV [3] RPOSO/RDATO [3] RCKO [3] TNEGI [3] TPOSI/TDATI [3] TCLK [3] VSS VDD RNEGO/BPV [2] RPOSO/RDATO [2] RCKO [2] TNEGI [2] TPOSI/TDATI [2] TCLK [2] RNEGO/BPV [1] RPOSO/RDATO [1] RCKO [1] TNEGI [1] TPOSI/TDATI [1] TCLK [1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 104 103
CN8380
128-Pin MQFP
102 101 100 99 98 97 96 95 94 93 92 85 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TRST VAA GND RAWMD [4] RRING [4] RTIP [4] VAAT [4] GNDT [4] XRING [4] XTIP [4] XOE [4] RAWMD [3] RRING [3] RTIP [3] VAAT [3] GNDT [3] XRING [3] XTIP [3] XOE [3] GNDR VAAR RAWMD [2] RRING [2] RTIP [2] VAAT [2] GNDT [2] XRING [2] XTIP [2] XOE [2] RAWMD [1] RRING [1] RTIP [1] VAAT [1] GNDT [1] XRING [1] XTIP [1] XOE [1] HM
LEGEND: [#] - Port Number (#) - Bit Number
8380_003
1-2
JATERR [4] JATERR [3] JATERR [2] JATERR [1] / SDO JDIR / SCLK JSEL(2) / SDI JSEL(1) / CS JSEL(0) IRQ RESET HTERM CLK_POL VSS VDD ZCS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. PTS(2) PTS(1) PTS(0)
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N8380DSA
CN8380
Quad T1/E1 Line Interface
Figure 1-2. CN8380 Logic Diagram (Host Mode)
1.0 Pin Descriptions
Host Mode Hardware
Hardware/Host Mode Hardware Reset Local Loopback Remote Loopback
Hardware/Host Mode Hardware Reset
Host Mode
HM I
I
RESET
RESET
HM
Control Hardware Interface
Control Interface
IRQ RLOS[1:4]
RLOS[1:4] IRQ
O Interrupt Request O Receive Loss of Signal Status
O Receive Loss of Signal Status O Interrupt Request
Local Loopback
I I I I I
I I
LLOOP[1:4]
Remote Loopback
RLOOP[1:4] SDI CS
LLOOP[1:4] RLOOP[1:4]
Serial Data In Serial Chip Select
Serial Clock In
Serial Data In
I I I
Serial Clock In
SCLK
SDI
SCLK CS
Serial Port Serial Port Interface Interface (SERIO)
SDO
SDO
O Serial Data Out
O
Serial Data Out
Serial Chip Select
(SERIO)
Receiver Receiver (RCVR) RCKO[1:4]
RCKO[1:4]
(RCVR)
O Receive Clock
O O O
Receive Clock Receive Positive Rail
Receive Tip Receive Ring
Receive Tip
I I
I I
RTIP[1:4]
RTIP[1:4] RRING[1:4]
RPOSO[1:4]
RPOSO[1:4]
O Receive Positive Rail O Receive Negative Rail
Receive Negative Rail
Receive Ring
RRING[1:4]
RNEGO[1:4]
RNEGO[1:4]
Transmit Clock PIO Transmit Clock PIO Transmit Positive Rail Transmit Positive Rail I I Transmit Negative Rail Transmit Negative Rail I I 1544 kHz All 1s Clock 1544 KHz All Ones Clock I I 2048 kHz All 1s Clock 2048 KHz All Ones Clock I I Transmit Output Enable Transmit Output Enable I I Transmit All 1s Transmit All Ones I I
TCLK[1:4] TCLK[1:4] TPOSI[1:4] TPOSI[1:4] TNEGI[1:4] TACKI TACKI EACKI EACKI XOE[1:4] XOE[1:4] TAIS[1:4] TAIS[1:4]
TNEGI[1:4]
Transmitter Transmitter (XMTR)
(XMTR)
XTIP[1:4] XTIP[1:4] XRING[1:4] XRING[1:4]
O Transmit Tip Transmit Tip O O Transmit Ring Transmit Ring O
Clock Rate Clock Rate Adapter (CLAD) Adapter (CLAD) CLAD Input CLAD Input I I
Reference Clock I I Reference Clock
CLADI CLADI
REFCKI REFCKI
CLK32 CLK32
CLK1544 CLK1544 CLK2048 CLK2048 CLADO CLADO
O 32.768 MHz Clock Out 32.768 MHz Clock Out O
O Line Rate Clock Out O T1T1 Line Rate Clock Out O Line Rate Clock Out O E1E1 Line Rate Clock Out CLAD Output O O CLAD Output
Test Test Clock In I I Clock In
Test Mode Select I I Test Mode Select
T TCK C K T TMS M S
Boundary Scan Boundary Scan (JTAG) (JTAG)
TDO TDO Test Data Out O O Test Data Out
Test Test Data In I Data In
I
TDI TDI
TR TRST S T
Test Test Reset In I I Reset In
8380_004
I = O = Output I = Input, Input, O = Output PIO =PIO = Programmable I/O Programmable I/O
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1-3
1.0 Pin Descriptions
CN8380
Quad T1/E1 Line Interface
Figure 1-3. CN8380 Logic Diagram (Hardware Mode)
Hardware Mode
VDD Hardware/Host Mode Hardware Reset I Jitter Attenuator Path I Jitter Attenuator Size I Unipolar/Bipolar I Transmitter Termination I Transmit Pulse Template I Clock Polarity Local Loopback I I Raw Mode Select I Remote Loopback I Zero Code Suppression I HM RESET JDIR JSEL(2:0) UNIPOLAR HTERM PTS(2:0) CLK_POL RAWMD[1:4] LLOOP[1:4] RLOOP[1:4] ZCS Receiver (RCVR) Receive Tip Receive Ring I I RTIP[1:4] RRING[1:4] Transmitter (XMTR) XTIP[1:4] XRING[1:4] O Transmit Tip O Transmit Ring RCKO[1:4] RPOSO[1:4] RNEGO[1:4] O Receive Clock O Receive Positive Rail O Receive Negative Rail IRQ JATERR[1:4] RLOS[1:4] O Interrupt Request O Jitter Attenuator Error Status O Receive Loss of Signal Status Hardware Control Interface
Transmit Clock
I
TCLK[1:4] TPOSI[1:4] TNEGI[1:4] TACKI EACKI XOE[1:4] TAIS[1:4]
Transmit Positive Rail I Transmit Negative Rail I 1544 kHz All 1s Clock I 2048 kHz All 1s Clock I Transmit Output Enable I Transmit All 1s I
Clock Rate Adapter (CLAD) CLK32 CLAD Input Reference Clock I I CLADI REFCKI CLK1544 CLK2048 CLADO Test Clock In Test Data In Test Reset In I I I TCK TMS TDI TRST Boundary Scan (JTAG) TDO O Test Data Out O 32.768 MHz Clock Out O T1 Line Rate Clock Out O E1 Line Rate Clock Out O 8 KHz Clock Out
Test Mode Select I
I = Input, O = Output PIO = Programmable I/O
1-4
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N8380DSA
8380_005
CN8380
Quad T1/E1 Line Interface
Table 1-1. Hardware Signal Definitions (1 of 5) Pin Label Signal Name I/O Receiver
RPOSO[1:4] RX Positive Rail (Bipolar Mode) RX Data (Unipolar Mode) O
1.0 Pin Descriptions
Definition
RDATO[1:4]
Line rate data output on the rising or falling edge of RCKO. The clock edge is determined by the CLK_POL pin in Hardware Mode or the CLK_POL register bit [RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high signal indicates receipt of a positive AMI pulse on RTIP/RRING inputs. In unipolar mode, RPOSO is redefined as RDATO and a high signal indicates either a positive or negative AMI pulse on RTIP/RRING inputs. RPOSO/RDATO is three-stated during device reset. Line rate data output on rising or falling edge of RCKO. The clock edge is determined by the CLK_POL pin in Hardware Mode or the CLK_POL register bit [RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high signal indicates receipt of a negative AMI pulse on RTIP/RRING inputs. In unipolar mode, RNEGO is redefined as BPV, and a high signal indicates the reception of a BPV which is not part of a ZCS code (B8ZS or HDB3). RNEGO/BPV is three-stated during device reset. Receive clock output. RCKO is the RPLL recovered line rate clock or jitter attenuated clock output, based on the programmed jitter attenuator selection. RCKO is three-stated during device reset. Differential AMI data inputs for direct connection to receive transformer.
RNEGO[1:4]
RX Negative Rail (Bipolar Mode) Bipolar Violation (Unipolar Mode)
O
BPV[1:4]
RCKO[1:4]
RX Clock Output
O
RTIP[1:4] RRING[1:4]
Receive Tip Receive Ring
I
Transmitter
TPOSI[1:4] Tx Positive Rail (Bipolar Mode) Tx Data (Unipolar Mode) Tx Negative Rail Input TX Clock Input I I/O I Positive rail, line rate data source for transmitted XTIP/XRING output pulses. Data is sampled on the falling edge of TCLK. In bipolar mode, a high on TPOSI causes a positive output pulse on XTIP/XRING; and a high on TNEGI causes a negative output pulse. In unipolar mode, TPOSI is redefined as TDATI and accepts single-rail NRZ data. TNEGI is not used in unipolar mode. Negative rail, line rate data input on TCLK falling edge. Refer to TPOSI signal definition. Transmit line rate clock. TCLK is the transmit clock for TPOSI and TNEGI data inputs and for transmitter timing. Normally, TCLK is an input and samples TPOSI/TNEGI on the falling edge. In Host Mode, TCLK can be configured as an output to supply a line rate transmit clock from the CLAD. The timing reference for the TCLK output (and CLAD) can be selected from six sources. Alternate T1 and E1 transmit clock used to transmit AIS (all 1s alarm signal) when the primary transmit clock source, TCLK, fails. TACKI (T1) or EACKI (E1) is either manually or automatically switched to replace TCLK [LIU_CTL; addr n3]. Systems without an AIS clock should connect TACKI and EACKI to ground. A low signal enables XTIP and XRING output drivers. Otherwise outputs are high impedance. In Hardware Mode, a low signal causes AIS (unframed all 1s) transmission on XTIP/XRING outputs. In Host Mode, these pins can be enabled or disabled [LIU_CTL; addr n3]. If disabled, they are not used and may be left unconnected.
TDATI[1:4]
TNEGI[1:4] TCLK[1:4]
TACKI
T1 AIS Clock
I
EACKI XOE[1:4] TAIS[1:4]
E1 AIS Clock Transmit Output Enable Transmit AIS Alarm
I IP IP
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1-5
1.0 Pin Descriptions
CN8380
Quad T1/E1 Line Interface
Table 1-1. Hardware Signal Definitions (2 of 5) Pin Label
XTIP[1:4] XRING[1:4]
Signal Name
Transmit Tip Transmit Ring
I/O
O
Definition
Complementary AMI transmitter line outputs for direct connection to transmit transformer. Optionally, both outputs are three-stated when XOE is high.
Clock Rate Adapter (CLAD)
CLADI CLAD Input I CLAD input timing reference used to phase/frequency lock the CLAD outputs to an input clock frequency selected in the range of 8 kHz to 32,768 kHz [CLAD_CR; addr 02]. Systems which do not use CLADI should connect CLADI to ground. In Hardware Mode, the CLAD timing reference automatically switches to internal free-run operation if clock edges are not detected on CLADI pin. System must apply a 10 MHz 50 ppm (E1) or + 32 ppm (T1) clock signal to act as the frequency reference for the internal numerically controlled oscillator (NCO). REFCKI determines the frequency accuracy and stability of the CLAD output clocks when operating in free-run mode [CLAD_CR; addr 02]. REFCKI is the baseband reference for all CLAD/JAT functions and is used internally to generate clocks of various frequency locked to a selected receive or external clock. Note: REFCKI is always required. CLK32 32 MHz Clock Output T1 Clock Output O Fixed rate 32.768 MHz clock output provided by the CLAD. May be used by framers, such as the CN8398 octal T1/E1 framer, to provide system timing reference. Fixed rate 1.544 MHz T1 line rate clock output provided by the CLAD. May be used for TCLK or TACKI clock sources. This clock is locked to the selected CLAD timing reference. Fixed rate 2.048 MHz E1 line rate clock output provided by the CLAD. May be used for TCLK or EACKI clock sources. This clock is locked to the selected CLAD timing reference. In Hardware Mode, CLADO is a fixed rate 8 kHz clock output provided by the CLAD. In Host Mode, CLADO may be configured to operate at one of 14 different clock frequencies [CSEL; addr 03] that include T1 or E1 line rates. CLADO is typically programmed to supply system clocks that are phase-locked to the selected receive or CLAD timing reference [CLAD_CR; addr 02].
REFCKI
Reference Clock
I
CLK1544
O
CLK2048
E1 Clock Output
O
CLADO
CLAD Output
O
Hardware Control Signals
HM Hardware Mode IP A high on HM places the device in Hardware Mode, enabling all hardware control pin functions. A low on HM places the device in Host Mode, disabling some hardware-mode-only pin functions and enabling the serial port signals on the dual function pins listed below. The serial port signals allow serial host access to the device registers. Refer to the Host Serial Control Signals section of this table. JSEL(1) / CS JDIR / SCLK RAWMD[1:4] Raw Mode IP JSEL(2) / SDI JATERR(1) / SDO
Low selects receiver Raw mode. Applicable only in Hardware Mode. In Raw mode, RPOSO and RNEGO represent the data slicer outputs and RCKO is the logical OR of RPOSO and RNEGO.
1-6
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N8380DSA
CN8380
Quad T1/E1 Line Interface
Table 1-1. Hardware Signal Definitions (3 of 5) Pin Label
RESET
1.0 Pin Descriptions
Signal Name
Hardware Reset
I/O
IP
Definition
Active low asynchronous hardware reset. A falling edge forces registers to their default, power-up state. Output pins are forced to the high impedance state while RESET is asserted. RESET is not mandatory at power-up because an internal power-on reset circuit performs an identical function. Applicable only in Hardware Mode. A high signal on UNIPOLAR configures all RPOSO outputs and TPOSI inputs to operate with unipolar, NRZformatted data. In this mode, RNEGO reports non-ZCS BPVs and TNEGI is not used. A low signal on UNIPOLAR configures all channels' RPOSO/RNEGO and TPOSI/TNEGI interfaces to operate with bipolar, dual-rail, NRZ formatted data. Applicable only in Hardware Mode. A high signal on ZCS enables the transmit ZCS encoder and the receive ZCS decoder if unipolar mode is enabled (UNIPOLAR = 1). In Bipolar Mode (UNIPOLAR = 0), the ZCS encoder and decoder are disabled and ZCS is ignored. Applicable only in Hardware Mode. High sets RPOSO/RNEGO to be output on the falling edge of RCKO. Low sets RPOSO/RNEGO to be output on the rising edge of RCKO Applicable only in Hardware Mode. The PTS(2:0) control bus selects the transmit pulse template and the line rate (T1 or E1) globally for all channels. Refer to the description of HTERM in this table and to the transmit pulse configurations in Table 2-3. Applicable only in Hardware Mode. If an external transmit termination resistor is used to meet return loss specifications; a transformer with a 1:2 turns ratio is used, and HTERM is set high to allow the transmitter to compensate for the increased load. Refer to the Transmitter section of this table and Tables 2-4 through 2-8 for transmitter termination configuration options. Active low, open drain output. In Host Mode, IRQ indicates one or more pending interrupt requests ([ISR; addr n6] and [CSTAT; addr 06]). In Hardware Mode, IRQ is the logical NOR of the four internal transmitter driver performance monitor outputs. Applicable only in Hardware Mode. The JSEL and JDIR pins determine the JAT configuration. JSEL(2:0) enables and selects the JAT depth as shown in the table below. SDI/JSEL(2) and CS /JSEL(1) are dual function pins. JSEL(2:0) 000 001 010 011 100 111 JAT Mode 8 bits 16 bits 32 bits 64 bits 128 bits Disable JAT
UNIPOLAR
Unipolar Mode Select
IP
ZCS
Zero Code Suppression Select Rx Clock Polarity Select Transmit Pulse Template Select
IP
CLK_POL
IP
PTS(2:0)
IP
HTERM
Transmitter Hardware Termination
IP
IRQ
Interrupt Request
OD
JSEL(2:0)
Jitter Attenuator Select
IP
JDIR
Jitter Attenuator Direction
IP
Applicable only in Hardware Mode. JDIR determines the path in which the JAT is inserted. If JDIR is low, the JAT (if enabled) is placed in the receive path; if high, the JAT (if enabled) is placed in the transmit path. Refer to the description for JSEL(2:0). SCLK/JDIR is a dual function pin. Applicable only in Hardware Mode. A high on JATERR indicates an overflow or underflow error in the jitter attenuator elastic store. JATERR(1) / SDO is a dual function pin.
JATERR[1:4]
Jitter Attenuator Error
O
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1.0 Pin Descriptions
CN8380
Quad T1/E1 Line Interface
Table 1-1. Hardware Signal Definitions (4 of 5) Pin Label
RLOS [1:4]
Signal Name
Receive Loss of Signal Local Loop Remote Loop
I/O
O
Definition
RLOS is asserted low when 100 (T1) or 32 (E1) consecutive 0s (no pulses) are received at the line interface or when the received signal level is approximately 18 dB below nominal for at least 1 ms. These pins are always enabled in Hardware Mode and may be enabled or disabled in Host Mode [LIU_CTL; addr n3]. A low on LLOOP initiates Local Analog Loopback and a low on RLOOP initiates Remote Line Loopback. Local Digital Loopback is initiated if both signals are asserted together.
LLOOP [1:4] RLOOP [1:4]
IP IP
Boundary Scan Signals (JTAG)
TDO Test Data Output O Test data output per IEEE Std. 1149.1-1990. Three-state output used for reading all serial configuration and test data from internal test logic. Updated on the falling edge of TCK. Test data input per IEEE Std. 1149.1-1990. Used for loading all serial instructions and data into internal test logic. Sampled on the rising edge of TCK. TDI may be left unconnected if not used. Active-low test mode select input per IEEE Std 1149.1-1990. Internally pulled-up input signal used to control the test logic state machine. Sampled on the rising edge of TCK. TMS may be left unconnected if not used. Test clock input per IEEE Std. 1149.1-1990. Used for all test interface and internal test-logic operations. If not used, TCK should be pulled low. Active low reset. TRST is pulled up internally and may be left unconnected if not used.
TDI
Test Data Input
IP
TMS
Test Mode Select
IP
TCK TRST
Test Clock Reset
IP IP
Host Serial Control Signals
CS SDI SDO SCLK Chip Select Serial Data In Serial Data Out Serial Clock IP IP O IP In Host Mode, CS is an active low input used to enable read/write access with the host serial control port. CS /JSEL(1) is a dual function pin. In Host Mode, SDI is the serial data input for the host serial control port. SDI/JSEL(2) is a dual function pin. In Host Mode, SDO is the serial data output for the host serial control port. SDO/JATERR[1] is a dual function pin. In Host Mode, SCLK is the serial clock input for the host serial control port. SCLK/JDIR is a dual function pin.
Power Supply Pins and No-Connect Pins
VAA GND VAAT[1:4] GNDT[1:4] VAAR GNDR Analog Supply Ground Tx Driver Supply Ground Rx Analog Supply Ground I I +3.3 V + 5%. Power supply pairs for the transmitter driver circuitry. These pin pairs should each be bypassed with a tantalum capacitor value of at least 10 F. + 3.3 V + 5%. Power supply pair for the analog receiver circuitry. I +3.3 V + 5%. Power supply pair for the analog circuitry.
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CN8380
Quad T1/E1 Line Interface
Table 1-1. Hardware Signal Definitions (5 of 5) Pin Label
VAACL GNDCL VDD VSS VGG
1.0 Pin Descriptions
Signal Name
CLAD Supply Ground Digital Supply Ground ESD Rail
I/O
I
Definition
+ 3.3 V + 5%. Power supply pair for the CLAD PLL circuitry.
I
+ 3.3 V + 5%. Power supply pairs for the digital circuitry.
I
To insure 5 V tolerance in mixed + 5 V / + 3.3 V systems, this input must be connected to + 5 V. If all logic input signals are 3.3 V levels, then this pin may be connected to the 3.3 V supply. No-connect pins are reserved for future device compatibility and should be left unconnected.
N.C.
NOTE(S):
No Connect
--
1. I/O Types: I = Standard input IP = Input with internal pull-up resister O = Standard output OD = Output with open drain 2. Legend: [#] = Port number (#) = Bit number
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CN8380
Quad T1/E1 Line Interface
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2
2.0 Circuit Description
2.1 Overview
The CN8380 includes four identical T1/E1 transceiver channels and a common CLAD packaged in a 128-pin MQFP carrier. It is designed to interface T1/E1 framers, or to operate as a stand-alone line interface for synchronous or plesiochronous mappers and multiplexers. The CN8380 is ideal for high line density, short-haul applications that require low power (3.3 V supply) operation. The configurable T1/E1 operation and common line interface design allows support for single-board T1 and E1 designs. Customer premise applications are supported by an on-chip JAT which conforms to AT&T PUB 62411 and a selectable transmit pulse shape which conforms to FCC Part 68, Pulse Option A. Selectable unipolar or bipolar interface options and internal ZCS encoding and decoding are useful in many multiplexer and mapper applications. In the most simple configuration, Hardware Mode, the device is controlled using dedicated hardware control pins. In this mode, the four channels are configured globally to identical operating modes (T1, E1, transmit termination, jitter attenuators, and so on). Each channel has device pins dedicated for channel control and status, such as loopback controls, bipolar/unipolar interface modes, and loss of signal indicators. Hardware Mode is selected by pulling the HM pin high. Host Mode allows control of the device through a 4-line serial port. In this mode, all control and status functions can be accessed using internal registers. Several additional features are also available in Host Mode, such as individual channel operating mode configuration (T1/E1, transmit termination, jitter attenuators, etc.) and programmable CLAD output frequencies. Host Mode is selected by grounding the HM pin. The CN8380 incorporates printed circuit board testability circuits in compliance with IEEE Std P1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture, commonly known as JTAG (Joint Test Action Group). A detailed block diagram is displayed in Figure 2-1.
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2-2
IRQ ZCS UNIPOLAR Control RLOS Detect Clock Recovery RPLL 1 0 0 1 RZCS Decode RPOSO[n] RNEGO[n] RCKO[n] RAWMD[n] CLK_POL SDO SDI CS SCLK RLOS[n] JATERR[n] JATERR[1] JSEL(2) JSEL(1) JSEL(0) JDIR VGA Adaptive Equalizer Peak Detect and Slicer Local Digital Loopback Jitter Attenuator Remote Line Loopback Note: Only one LUI is shown. The other three are identical. 8X TPLL 1 DRV 0 0 Clock Mon DAC 1 Pulse Shape AIS Gen TZCS Encode TPOSI[n] TNEGI[n] TCLK[n] TACKI EACKI Control CLADI REFCKI JTAG RCKO[1] RCKO[2] RCKO[3] RCKO[4] Phase Detector NCO Divider Chain CLAD CLK32 (32.768 MHz) CLK2048 (2.048 MHz) CLK1544 (1.544 MHz) CLADO TAIS[n] TDI TDO TMS TCLK TRST RLOOP[n]
2.1 Overview
2.0 Circuit Description
LLOOP[n]
Figure 2-1. Detailed Block Diagram
RTIP[n] RRING[n]
0
1
Local Analog Loopback
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XTIP[n] XRING[n]
DPM
Short CKT Detect
HM XOE[n] HTERM PTS(2:0)
8380_006
CN8380
Quad T1/E1 Line Interface
N8380DSA
CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.2 Configuration and Control
2.2 Configuration and Control
2.2.1 Hardware Mode
In Hardware Mode, the device is controlled using dedicated hardware control pins. In this mode, the four channels are configured globally to identical operating modes (T1, E1, transmit termination, jitter attenuators, and so on). Each channel has device pins dedicated for channel control and status, such as loopback controls, bipolar/unipolar interface modes, and loss of signal indicators. Refer to Table 1-1, Hardware Signal Definitions, for a description of all hardware pins. Hardware Mode is selected by pulling the HM pin high.
2.2.2 Host Mode
In Host Mode, control of the device is through a four-line serial port. In this mode, all control and status functions can be accessed using internal registers. Refer to Chapter 3.0, Registers, for a description of each register. Host Mode is selected by grounding the HM pin.
2.2.3 Host Serial Control Interface
The CN8380 serial interface is a four-wire, slave interface which allows a host processor or framer with a compatible master serial port to communicate with the LIU. This interface allows the host to control and query the CN8380 status by writing and reading internal registers. One 8-bit register in the LIU can be written via the SDI pin or read from the SDO pin at the clock rate determined by SCLK. The serial port is enabled by pulling the chip select pin, CS, active (low) during the read and write cycles. Refer to Figure 2-2 for host serial port signals. The serial interface uses a 16-bit process for each write or read operation. During a write or read operation, an 8-bit control word, consisting of a read/write control bit (R/W) and a 7-bit LIU register address (A[6:0]) is transmitted to the LIU using the SDI pin. If the operation is a write operation (R/W = 0), an 8-bit register data (D[7:0]) byte follows the address on the SDI pin. This data is received by the CN8380 and stored in the addressed register. If the operation is a read operation (R/W = 1), the CN8380 outputs the addressed register contents on the SDO pin. The signal input on SDI is sampled on the SCLK falling edge, and data output on SDO changes on the SCLK rising edge.
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2.2 Configuration and Control
CN8380
Quad T1/E1 Line Interface
Figure 2-2. Host Serial Port Signals
Read Timing
CS
SCLK
SDI
R/W A0
A1
A2
A3
A4
A5
A6
Address/Control Byte SDO D0 D1 D2 D3 D4 D5 D6 D7
Register Data Byte
Write Timing
CS
SCLK
SDI
R/W A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
Address/Control Byte SDO
8380_007
Register Data Byte
2.2.4 Reset
The CN8380 supports three reset methods: power-on reset, hard reset initiated by the RESET pin, and soft reset initiated by the RESET bit in the Global Configuration Register [GCR; addr 01]. In Host Mode, all three reset methods produce the same results as listed below. In Hardware Mode, power-on reset and hard reset produce the same results as shown; and soft reset is not applicable. After RESET is complete, the following is true: Hardware Mode Digital receiver outputs (RPOSO[1:4] and RNEGO[1:4], RCKO[1:4]) are enabled. Transmitter line outputs (XTIP[1:4] and XRING[1:4]) are enabled (controlled by XOE). Host Mode Digital receiver outputs (RPOSO[1:4] and RNEGO[1:4], RCKO[1:4]) are three-stated. Transmitter line outputs (XTIP[1:4] and XRING[1:4]) are three-stated.
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Quad T1/E1 Line Interface
2.0 Circuit Description
2.2 Configuration and Control
Hardware Mode CLK1544, CLK2048, and CLADO clock outputs are enabled. Transmitter clocks, TCLK[1:4], are configured as inputs. The IRQ pin is enabled (controlled by DPM).
Host Mode CLK1544, CLK2048, and CLADO clock outputs are three-stated. Transmitter clocks, TCLK[1:4], are configured as inputs. The IRQ pin is three-stated.
All interrupt sources are disabled. All configuration registers are set to default values as listed in Section 3.1, Address Map. 2.2.4.1 Power-on Reset An internal power-on reset process is initiated during power-up. When VDD has reached approximately 2.6 V the internal reset process begins and continues for , 300 ms maximum if REFCLK is applied. If REFCLK is not present, the CN8380 remains in the reset state. Hard reset is initiated by bringing the RESET pin active (low). Once initiated, the internal reset process completes in 5 s maximum. If the RESET pin is held active continuously, the clock and data outputs and the IRQ pin remain three-stated. The following output pins are forced to high impedance while RESET is held active: RPOSO[1:4] RNEGO[1:4] RCKO[1:4] XTIP[1:4] XRING[1:4:] CLK1544 CLK2048 2.2.4.3 Soft Reset CLADO TCLK[1:4]
IRQ RLOS[1:4]
2.2.4.2 Hard Reset
JATERR[1:4] SDO TDO
In Host Mode, soft reset is initiated by writing a one to the RESET bit in the Global Configuration register [addr 01]. The RESET bit is self-clearing. Once initiated, the internal reset process completes in 5 s maximum and the device enters normal operation.
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2.3 Receiver
CN8380
Quad T1/E1 Line Interface
2.3 Receiver
Bipolar AMI pulses are input on the receiver input pins, RTIP[n] and RRING[n]. The receiver recovers clock and data from the AMI signal which has been attenuated and distorted due to the line characteristics. The AMI pulses are converted into bipolar or unipolar, NRZ data and output on RPOSO[n] and RNEGO[n], along with the recovered clock on RCKO[n]. Figure 2-3 illustrates the relationship between the AMI received signal, the recovered clock, and the data outputs. This section discusses each receiver block from the line input to the digital outputs.
Figure 2-3. Receiver Signals
Data Slicer Level (50% of Peak) Internal Equalized Received Signal RCKO
BPV RPOSO (Bipolar) RNEGO (Bipolar)
RDATO (Unipolar) 1 BPV (Unipolar) 1 1 0 1 1 0 1 1
8380_008
2.3.1 Data Recovery
The receiver recovers data by normalizing the input signal with an automatic gain control (AGC) circuit, removing distortion with an equalizer, and extracting the data using a data slicer. The transfer function of the equalizer is adjusted based on the average peak value of the input signal. The AGC maintains the equalizer's average peak output level to a constant value. The data slicer compares the equalizer output to a threshold value equal to 50% of the average peak equalizer output level and produces both positive and negative pulse detect signals. The data slicer outputs are re-timed using the recovered clock and routed to the RZCS decoder (or to the JAT).
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Quad T1/E1 Line Interface
2.0 Circuit Description
2.3 Receiver
2.3.1.1 Raw Receive Mode
Optionally, the data slicer outputs, before re-timing, can be routed directly to the RPOSO and RNEGO digital output pins. This option (raw receive mode) is selected by asserting the RAWMD[n] pin in Hardware Mode or by asserting the RAWMD register bit [RLIU_CR; addr n1] in Host Mode. In raw receive mode, RCKO is replaced by the logical OR of the RPOSO and RNEGO output signals. This mode is useful in applications which provide external clock and data recovery. Figure 2-4 illustrates the raw mode receiver signals.
Figure 2-4. Raw Mode Receiver Signals
Data Slicer Level (50% of Peak) Internal Equalized Received Signal
BPV RPOSO (RAW Mode) RNEGO (RAW Mode) RCKO (RAW Mode)
8380_009
2.3.1.2 Sensitivity
The receiver is capable of recovering signals with cable attenuation in the range of +3 to -12 dB in E1 and T1 modes. The receiver is configured by setting register bits appropriately in Host Mode or by setting configuration pins in Hardware Mode. See Table 2-1for line compatible modes.
Table 2-1. Line Compatible Modes Mode
T1 T1/E1 20 dB Bridge E1
Receiver Sensitivity
+3 dB to -12 dB -17 dB to -26 dB +3 dB to -12 dB
RALOS Threshold
-18 dB NA -18 dB
Squelch Threshold
-18 dB NA -18 dB
RLOS Detect
100 zeros 100 zeros 32 zeros
2.3.1.3 Bridge Mode
In Host Mode, the receiver allows interfacing to network test (MON) points which are resistively attenuated with resisters in series with transmit and receive Tip and Ring signals. The Bridge Monitor Level is -20 dB. Bridge operation is enabled by setting register bit ATTEN [addr n1] to 1. In this mode, RALOS detection and squelch operation are disabled.
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2.3 Receiver
CN8380
Quad T1/E1 Line Interface
2.3.1.4 Loss Of Signal Detector
The Receive Loss of Signal (RLOS) Detector monitors both consecutive 0s and signal level. Receive Analog Loss Of Signal (RALOS) is declared when RTIP/RRING input signal amplitude is a certain level (RALOS level) below the nominal receive level for at least 1 ms (2 ms maximum). RALOS status is cleared as soon as pulses above the RALOS level are detected. In Host Mode, the received data can be replaced with all 0s (squelched) if the receive level is also below the SQUELCH level. Squelch is enabled in register RLIU_CR [addr n1]. In Host Mode, RALOS real time status is reported in the ALARM [addr n5] register; and an interrupt status bit is available in the ISR [addr n6] register. Also, RALOS is indicated on the RLOS[n] pin, which is the logical NOR of the RLOS[n] status and RALOS[n] status. RLOS is declared when 100 (T1) or 32 (E1) consecutive bits with no pulses are detected. RLOS status is cleared when pulses are received with at least 12.5% pulse density (during a period of 192 bits starting with the receipt of a pulse) and where no occurrences of 100 or 32 consecutive bits with no pulses are detected. In Host Mode, RLOS real time status is reported in the ALARM register [addr n5]; and an interrupt status bit is available in the ISR register [addr n6]. Also, RLOS is indicated by a 0 level on the RLOS[n] pin, which is the logical NOR of the RLOS[n] status and RALOS[n] status.
2.3.2 Clock Recovery
2.3.2.1 Phase Lock Loop The Receive Phase Lock Loop (RPLL) recovers the line rate clock from the data slicer dual-rail outputs. The RPLL generates a recovered clock that tracks jitter in the data and sustains the data-to-clock phase relationship in the absence of incoming pulses. The RPLL is a digital PLL which adjusts its output phase in 1/16 unit interval (UI) steps. Consequently, the RPLL adds approximately 0.12 UI peak-to-peak jitter to the recovered receive clock. During loss of signal (RLOS or RALOS), the RPLL maintains an output clock signal and smoothly transitions to a nominal line rate frequency determined by the CLAD input reference (selected by CMUX [GCR; addr 01] or FREE [CLAD_CR; addr 02]). If the CLAD reference is the recovered received clock from a channel which has detected RLOS, the CLAD outputs and the recovered received clock enter a "hold-over" state to maintain the average frequency that was present just before the RLOS was detected. Figure 2-8, Receiver Input Jitter Tolerance, illustrates the receiver's jitter tolerance for all jitter attenuator (JAT) configurations: JAT disabled and JAT enabled in the receive path with each JAT elastic store size. The jitter tolerance of the clock and data recovery circuit alone (not including the JAT) is illustrated by the curve labeled with "JAT Disabled." The receiver meets jitter tolerance specifications TR62411, G.823, and G.824. In addition, the receiver meets jitter tolerance tests defined in ETS300 011: ISDN; Primary Rate User-Network Interface Layer 1 Specification and Test Principles.
2.3.2.2 Jitter Tolerance
2.3.3 Receive Jitter Attenuator
The data slicer outputs can be routed to the JAT before going to the RZCS decoder. The JAT attenuates clock and data jitter introduced by the line or added by the clock recovery circuit. The JAT can be placed in the receive path or transmit path, but not in both simultaneously. If the JAT is placed in the receive
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Quad T1/E1 Line Interface
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2.3 Receiver
path, RCKO is replaced with the jitter attenuated clock. The JAT performance is discussed in Section 2.6, Jitter Attenuator. In Host Mode, the JAT is configured for each channel independently and is put in the receive path by setting JEN and JDIR register bits to 1 [JAT_CR; addr n0]. In Hardware Mode, the JAT is configured for all channels globally using the JSEL(2:0) and JDIR pins. Refer to Chapter 1.0, Pin Descriptions for details.
2.3.4 RZCS Decoder
The RZCS decoder decodes the dual-rail data from the data slicer or from the JAT. In T1 mode, the RZCS decoder replaces received B8ZS codes with eight 0s. In E1 mode, HDB3 codes are replaced with four 0s. The B8ZS code is 000VB0VB and the HDB3 code is X00V; where B is a normal AMI pulse, V is a bipolar violation, and X is a don't-care. ZCS decoding (and encoding) can be enabled only if the digital interface mode is unipolar. In Host Mode, RZCS decoding (and TZCS encoding) is enabled for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to 1. In Hardware Mode, ZCS encoding/decoding is controlled globally for all channels by pulling the ZCS pin high. For the Hardware Mode pin definition, see Table 1-1.
2.3.5 Receive Digital Interface
The digital receiver outputs are provided on the RPOSO[n], RNEGO[n], and RCKO[n] pins, where [n] is channel number 1 to 4. The receiver outputs can be configured to operate in two modes: Bipolar NRZ format or unipolar NRZ format. In both modes, RPOSO[n] and RNEGO[n] outputs are clocked by RCKO[n], the recovered line rate clock, or the jitter attenuated clock if the JAT is enabled in the receive path. RCKO[n] polarity is configurable by the CLK_POL pin in Hardware Mode or register bit CLK_POL [RLIU_CR; addr n1] in Host Mode. RPOSO[n], RNEGO[n], and RCKO[n] are three-stated during device reset. 2.3.5.1 Bipolar Mode In bipolar mode, RPOSO/RNEGO signals output received data in bipolar dual-rail format, where a high level on RPOSO indicates receipt of a positive AMI pulse, and a high level on RNEGO indicates receipt of a negative AMI pulse on RTIP/RING inputs. In bipolar mode, the RZCS decoder is not available. In Hardware Mode, bipolar operation is enabled globally for all channels by pulling the UNIPOLAR pin low. In Host Mode, bipolar operation is enabled per channel by writing a 0 to register bit UNIPOLAR [RLIU_CR; addr n1]. In unipolar mode, RPOSO/RNEGO signals are replaced by RDATO/BPV signals. AMI encoded received data is decoded and output on RDATO in NRZ format, and BPV indicates that the currently received bit is a bipolar violation. If the RZCS decoder is enabled, the BPV pin indicates only bipolar violations which are not part of a ZCS code (B8ZS or HDB3). In Hardware Mode, unipolar operation is enabled by pulling the UNIPOLAR pin high. In Host Mode, unipolar operation is enabled by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].
2.3.5.2 Unipolar Mode
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2.4 Transmitter
CN8380
Quad T1/E1 Line Interface
2.4 Transmitter
Bipolar or unipolar, NRZ digital transmit data are input on TPOSI and TNEGI using the transmit clock TCLK. Data are converted into AMI pulses, shaped according to required standards, and transmitted to the line. Figure 2-5 illustrates the relationship between the AMI transmitted signal, the transmit clock, and the data inputs. This section discusses each transmitter block, from the digital inputs to the line output.
Figure 2-5. Transmitter Signals
TCLK
TPOSI (Bipolar) TNEGI (Bipolar)
TDATI (Unipolar) 1 1 0 Throughput Delay XTIP, XRING
8380_010
1
1
0
0
1
2.4.1 Transmit Digital Interface
The digital transmitter inputs, TPOSI[n] and TNEGI[n], accept bipolar or unipolar NRZ formatted data for transmission and are sampled by the falling edge of TCLK[n], where [n] is channel number 1 to 4. TCLK[n] is the line rate transmit clock and is normally supplied externally from a line rate source, but can also be sourced internally (only in Host Mode) from the CLAD. If sourced internally, TCLK[n] is configured as an output to provide the line rate clock to external circuitry. TCLK[n] direction is configured globally for all channels by writing to register bit TCLK_I/O [GCR; addr 01]. 2.4.1.1 Bipolar Mode In bipolar mode, TPOSI/TNEGI inputs accept bipolar dual-rail transmit data where a high on TPOSI causes a positive output pulse and a high on TNEGI causes a negative output pulse on XTIP/XRING. In this mode, the TZCS encoder is not available. In Hardware Mode, bipolar operation is enabled globally for all channels by pulling the UNIPOLAR pin low. In Host Mode, bipolar operation is
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Quad T1/E1 Line Interface
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2.4 Transmitter
enabled per channel by writing a 0 to register bit UNIPOLAR [RLIU_CR; addr n1]. 2.4.1.2 Unipolar Mode In unipolar mode, TPOSI is replaced with TDATI and accepts unipolar NRZformatted transmit data. TNEGI is not used in this mode. A high on TDATI causes an AMI pulse to be transmitted to the line. In this mode, the TZCS encoder can be enabled to provide B8ZS or HDB3 zero code suppression. In Hardware Mode, unipolar operation is enabled globally for all channels by pulling the UNIPOLAR pin high. In Host Mode, unipolar operation is enabled per channel by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].
2.4.2 TZCS Encoder
If enabled, the TZCS encoder encodes unipolar transmit data on TDATI with B8ZS (T1) or HDB3 (E1) line coding. In T1 mode, eight consecutive 0s are replaced with 000VB0VB; and in E1 mode, four consecutive 0s are replaced with X00V; where B is a normal AMI pulse, V is a bipolar violation, and X is a Don't Care. These are standard T1 and E1 line code options. ZCS encoding (and decoding) can be enabled only if the digital interface mode is unipolar. In Host Mode, TZCS encoding (and RZCS decoding) is enabled for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to 1. In Hardware Mode, ZCS encoding/decoding is controlled globally for all channels by pulling the ZCS pin high. For the Hardware Mode pin definition, refer to Table 1-1.
2.4.3 Transmit Jitter Attenuator
Transmit data from the TZCS encoder can be routed to the JAT before going to the AIS Generator. The JAT attenuates clock and data jitter from the transmit inputs or from the receiver if Remote Line Loopback (RLL) is active. The JAT can be placed in the receive path or transmit path, but not both simultaneously. If the JAT is placed in the transmit path, the jitter attenuated clock becomes the transmit clock for downstream circuits. In Host Mode, the JAT is configured for each channel independently and is put in the transmit path by setting the JEN register bit to 1 and the JDIR register bit to 0 [JAT_CR; addr n0]. In Hardware Mode, the JAT is configured for all channels globally using the JSEL(2:0) and JDIR pins. For pin definitions, refer to Chapter 1.0, Pin Descriptions; for JAT transfer characteristics, refer to Figure 2-9; and for more information on loopbacks, refer to Section 2.5, Loopbacks.
2.4.4 All 1s AIS Generator
The transmit data can be replaced with unframed all 1s for transmitting the alarm indication signal (AIS). This includes replacing data supplied from TPOSI[n]/TNEGI[n] pins and from the receiver during RLL. AIS transmission does not affect transmit data that is looped back to the receiver during Local Digital Loopback (LDL). This allows LDL to be active simultaneously with the transmission of AIS. AIS is used to maintain a valid signal on the line and to inform downstream equipment that the transmit data source has been lost. AIS transmission can be done manually or automatically when loss of transmit clock is detected. A clock monitor circuit allows manual or automatic switching of the transmit clock to an alternate AIS clock.
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2.0 Circuit Description
2.4 Transmitter
CN8380
Quad T1/E1 Line Interface
In Hardware Mode, AIS can be controlled only manually by pulling the
TAIS[n] hardware pin low. If TCLK[n] is present, then it is used to transmit AIS.
If TCLK[n] is not present (for two clock periods), the alternate AIS clock on either TACKI (T1 Mode) or EACKI (E1 Mode) is used. The AIS transmit clock switches back to TCLK[n] when the TCLK[n] signal returns. In Host Mode, AIS can be transmitted using the TAIS[n] hardware pins or the TAIS register bit, or automatically by enabling the AUTO_AIS register bit. AIS clock switching can be enabled by using the AISCLK register bit. Setting AISCLK to 1 forces the use of the alternate AIS clock on either TACKI (T1 Mode) or EACKI (E1 Mode) pins when transmitting AIS. If AUTO_AIS is set to 1, AIS is automatically transmitted when the clock monitor detects loss of clock on TCLK[n]. When using automatic AIS transmission, the user should also enable the AISCLK bit and provide an alternate clock source to insure that AIS will be transmitted. CLAD output clocks CLK2048 and CLK1544 can be connected externally to EACKI and TACKI alternate AIS clock inputs for this purpose. Setting register bit TAIS_PE to 1 disables the TAIS register bit and allows manual transmission of AIS using the TAIS[n] hardware pins. Refer to LIU_CTL [addr n3] in Chapter 3.0, Registers, and to Table 1-1, Hardware Signal Definitions. If TAIS is activated when Remote Line Loopback is active, AIS is transmitted using the received clock (or JCLK if the JAT is enabled in the receive direction). Table 2-2 lists transmitter operating modes resulting from various configuration settings and input conditions.
Table 2-2. Transmitter Operating Modes Configuration and Input Status RLOOP (W/LLOOP=0)
0 0 0
Transmitter Mode AISCLK
X 0 1
TLOC
X X X
TAIS
0 1 1
AUTO_AIS
0 X X
Transmit Data
Tx Data AIS AIS
Transmit Clock
TCLK TCLK TACKI/EACKI
0 0 0
0 1 1
0 0 0
1 1 1
X 0 1
Tx Data AIS AIS
TCLK TCLK TACKI/EACKI
1 1
NOTE(S): X is don't-care.
X X
0 1
X X
X X
Rx Data AIS
RCLK RCLK
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CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.4 Transmitter
2.4.5 Pulse Shaper
All transmit pulse shaping to meet E1 and T1 transmission standards is done internally, eliminating the need for external shaping circuitry. The pulse shape block receives bipolar NRZ transmit data, produces a set of eight 5-bit values which define the pulse shape, and converts the shape values into an analog pulse using a DAC. Table 2-3 lists the transmit pulse template selections and applications.
Table 2-3. Transmit Pulse Configurations Application Line Rate
T1 DSX-1 T1.102 CB119 100 Twisted Pair T1 T1 T1 T1 ITU-T G.703 75 Coaxial Cable ITU-T G.703 120 Twisted Pair FCC Part 68 Opt A I.431 100 Twisted Pair E1 E1 T1
Line Length
0-133 ft. 133-266 ft. 266-399 ft. 399-533 ft. 533-655 ft. -- -- --
Hardware Mode Configuration PTS(2:0)
000 001 010 011 100 101 110 111
Host Mode Configuration [TLIU_CR; addr n2] PULSE(2:0)
000 001 010 011 100 101 110 111
In Hardware Mode, standard pulse templates are selected globally for all channels using hardware pins PTS(2:0). Refer to the Chapter 1.0, Pin Descriptions, and Table 1-1, Hardware Signal Definitions.
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2.4 Transmitter
CN8380
Quad T1/E1 Line Interface
In Host Mode, standard pulse templates are selected per channel by writing to register bits PULSE(2:0) [TLIU_CR; addr n2]. If desired, custom pulse shapes can be programmed for each channel using the SHAPEn [addr n8 - nF] registers and the PPT [TLIU_CR; addr n2] register bit. The data written into the SHAPEn registers is 5-bit magnitude only. The first four code values of the pulse define the first half of the symbol, and the last four values define the last half of the symbol. The last half symbol polarity is always forced to be opposite from the first half polarity. Figure 2-6 illustrates the shaped transmit signals.
Figure 2-6. Transmit Pulse Shape
TCLK 8 x TCLK Shape Data Magnitude (0x00-0x1F)
Digitized AMI Pulses
Positive Pulse
8380_011
Negative Pulse
2.4.6 Driver
The transmit DAC converts digitally shaped AMI pulses into analog bipolar signals. The line driver provides a high impedance, current drive for the transmit DAC and outputs transmit signals to the XTIP[n] and XRING[n] output pins. The high impedance driver allows line impedance matching using external parallel resistors to meet return loss requirements. In applications which require surge protection, pulse amplitude compensation is provided if protection resistors are needed in series with XTIP[n] and XRING[n]. When a shorted line is detected, transmit monitor and protection circuits reduce the output current level to less than 50 mA peak. The standard transmit transformer for the CN8380 has a turns ratio of 1:2 (chip-side: line-side). To minimize power consumption, an alternate 1:1.36 turns ratio transformer can be used in an unterminated configuration. 2.4.6.1 Transmit Termination Options Various transmitter termination options are available to meet almost any interface requirement. Figure 2-7 illustrates the location of the transmit termination components. In this figure, Ct is a smoothing capacitor across XTIP and XRING. The recommended value for Ct is 150 pF. If other components are also connected to XTIP/XRING, such as surge protection diodes, Ct's value should be adjusted to maintain a total parallel capacitance of approximately 150 pF. Rt is a parallel termination resistor selected to provide the required transmitter return loss, typically -18 dB. If an application does not have a return loss requirement, Rt can be omitted in order to reduce total power consumption.
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CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.4 Transmitter
The standard transformer recommended has a turns ratio of 1:2. This turns ratio is required if parallel termination (Rt) or series resistors (Rs) are desired. The alternate transformer has a turns ratio of 1:1.36. This transformer can be used only if all of the following are true: * * * Parallel termination (Rt) is not used. Series resistors (Rs) are not used. T1 DSX-1 transmit pulse is not used.
Refer to Option E in Table 2-7 below. Transmitter power consumption is reduced by approximately 30%, compared to the unterminated, standard transformer configuration. Resistors (Rs) in series with Tx TIP and Tx RING line connections are sometimes used with surge protection circuits. Without compensation, the addition of these resistors decreases the transmit pulse amplitude. The CN8380 provides an option in Host Mode to boost the output level if resistors are installed. Compensation is optimized for the use of 5.6 Rs values. In Hardware Mode, these resistors are required.
Figure 2-7. Transmit Termination Components
1:N XTIP CN8380 XRING Transformer Ct Rt
Rs Tx TIP
Rs Tx RING
8380_012
Tables 2-4 through 2-8 provide recommended termination component values and CN8380 configuration information for all termination options supported. The resulting return loss value is also listed. All five options are supported in Host Mode, whereas only options C and D are supported in Hardware Mode. Before selecting a termination option, refer to Table 2-3, Transmit Pulse Configurations, to select an application mode. Then refer to the Transmit Termination tables below to select a termination option.
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2.0 Circuit Description
2.4 Transmitter Option A
CN8380
Quad T1/E1 Line Interface
Option A uses the standard 1:2 transformer, no series protection resistors (Rs), and no parallel termination (Rt) for T1 applications. In E1 applications, Rt is included because it is usually required to provide a minimal level of line impedance matching.
Table 2-4. Transmit Termination Option A Application
T1--DSX-1 E1--75 E1--120 T1-- I.431
NOTE(S):
Series Resistors (Rs)
None None None None
Parallel Termination (Rt, )
None 126.4 204.4 None
Return Loss (dB)
0 -10 -10 0
1. Standard Transformer (1:2 turns ratio) 2. Hardware Mode: HTERM=0 3. Host Mode: ALT_TR = 0, TERM = 0, T_BOOST = 0 [TLIU_CR; addr n2]
Option B
Option B uses the standard 1:2 transformer and no series protection resistors (Rs). A common parallel termination (Rt) for both T1 and E1 applications is included to provide line impedance matching.
Table 2-5. Transmit Termination Option B Application
T1--DSX-1 E1--75 E1--120 T1-- I.431
NOTE(S):
Series Resistors (Rs)
None None None None
Parallel Termination (Rt, )
23.7 23.7 23.7 23.7
Return Loss (dB)
-30 -18 -18 -30
1. Standard Transformer (1:2 turns ratio) 2. Hardware Mode: Not applicable 3. Host Mode: ALT_TR = 0, TERM = 1, T_BOOST = 0 [TLIU_CR; addr n2]
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CN8380
Quad T1/E1 Line Interface
Option C
2.0 Circuit Description
2.4 Transmitter
Option C uses the standard 1:2 transformer and no parallel termination (Rt) for T1 applications. In E1 applications, Rt is included because it is usually required to provide a minimal level of line impedance matching. Series protection resistors (Rs) are included. Option C is available only in Host Mode.
Table 2-6. Transmit Termination Option C Application
T1--DSX-1 E1--75 E1--120 T1--I.431
NOTE(S):
Series Resistors (Rs)
2 x 5.6 2 x 5.6 2 x5.6 2 x 5.6
Parallel Termination (Rt, )
None 114.8 190.0 None
Return Loss (dB)
0 -10 -10 0
1. Standard Transformer (1:2 turns ratio) 2. Hardware Mode: HTERM = 0 3. Host Mode: ALT_TR = 0, TERM = 0, T_BOOST = 1 [TLIU_CR; addr n2]
Option D
Option D uses the standard 1:2 transformer. A common parallel termination (Rt) for both T1 and E1 applications is included to provide line impedance matching. Series protection resistors (Rs) are also included. Option D is available in both Host Mode and Hardware Mode.
Table 2-7. Transmit Termination Option D Application
T1--DSX-1 E1--75 E1--120 T1--I.431
NOTE(S):
Series Resistors (Rs)
2 x 5.6 2 x 5.6 2 x 5.6 2 x 5.6
Parallel Termination (Rt, )
21 21 21 21
Return Loss (dB)
-30 -18 -18 -30
1. Standard Transformer (1:2 turns ratio) 2. Hardware Mode: HTERM = 1 3. Host Mode: ALT_TR = 0, TERM = 1, T_BOOST = 1 [TLIU_CR; addr n2]
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2.4 Transmitter Option E
CN8380
Quad T1/E1 Line Interface
Option E uses the alternate 1:1.36 transformer, no series protection resistors (Rs), and no parallel termination (Rt) for T1 applications. In E1 applications, Rt is included because it is usually required to provide a minimal level of line impedance matching. Option E is available only in Host Mode and cannot be used with DSX-1 applications.
Table 2-8. Transmit Termination Option E Application
E1--75 E1--120 T1--I.431
NOTE(S):
Series Resistors (Rs)
None None None
Parallel Termination (Rt, )
68.1 107.0 None
Return Loss (dB)
-10 -10 0
1. Alternate transformer (1:1.36 turns ratio) 2. Hardware Mode: Not Applicable 3. Host Mode: ALT_TR = 1, TERM = 0, T_BOOST = 0 [TLIU_CR; addr n2]
2.4.6.2 Output Disable
The transmitter analog outputs, XTIP[n] and XRING[n], are enabled per channel by pulling the XOE[n] pins low and are three-stated by pulling the XOE[n] pins high. In Host Mode, the PDN [TLIU_CR; addr n2] register bit also controls the XTIP[n] and XRING[n] outputs. A device RESET sets the PDN bits, thereby disabling XTIP[n] and XRING[n]. User software must clear PDN to enable the transmitter outputs. In Hardware Mode, the transmitter outputs are disabled while RESET is held active (low). When RESET is deactivated, XOE[n] controls the transmitter outputs. If the transmit driver is disabled (XOE[n] = 1), the driver performance monitor (DPM) is available for monitoring a transmit signal from an external source. Refer to Section 2.4.7.2, Driver Performance Monitor.
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CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.4 Transmitter
2.4.7 Transmitter Output Monitoring
2.4.7.1 Short Circuit Detect The transmitter output pulse is monitored and a short circuit is detected when the amplitude falls below an internally determined threshold for approximately 64-bit times. The short circuit state deactivates when the amplitude rises above a second threshold for 64-bit times. When a short is detected, the line driver current is reduced to approximately 50 mA peak, as measured on the line side of the transformer. Typically, this is caused by a transmit cable short circuit or by a transmission line transient current surge. In Host Mode, short circuit activation sets the TSHORT bit in the Alarm Status register [ALARM; addr n5] and in the Interrupt Status Register [ISR; addr n6]. No indication of short circuit is available in Hardware Mode. The DPM monitors the line driver output signal for valid signaling activity. The output signal is monitored for pulse level, invalid AMI coding, pulse density, and stuck signals. In Host Mode, a DPM fault condition sets the TLOS bit in the Alarm Status register [ALARM; addr n5] and in the Interrupt Status Register [ISR; addr n6]. In Hardware Mode, the four internal DPM status indicators are combined (logical NOR) and output on the IRQ pin. If the transmit driver is disabled (XOE = 1), the DPM is available for monitoring a transmit signal from an external source. In this mode, XTIP[n] and XRING[n] are used as inputs and can be connected to the transmit outputs of another CN8380 channel or device.
2.4.7.2 Driver Performance Monitor
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2.5 Loopbacks
CN8380
Quad T1/E1 Line Interface
2.5 Loopbacks
Three per-channel loopbacks are provided for system diagnostic testing: Local Analog Loopback, Local Digital Loopback, and Remote Line Loopback. Loopbacks can be controlled by either hardware pins or internal register bits. For hardware control, two dedicated pins--LLOOP and RLOOP--are provided. If configured in Host Mode, register bits are provided for loopback control. In addition, the LLOOP and RLOOP pins can be enabled by register bits so that loopbacks can be controlled by the hardware pins even in Host Mode. Loopback controls are detailed in Table 2-9. Refer also to register LIU_CTL [addr n3] in Chapter 3.0, Registers.
Table 2-9. Loopback Control Pins LLOOP
1 1 0 0
RLOOP
1 0 1 0 None Remote Line Loop Local Analog Loop Local Digital Loop
Loopback
2.5.1 Local Analog Loopback
Local Analog Loopback (LAL) causes the transmit data and clock inputs (TPOSI/TNEGI and TCLK) to be looped back to the receiver outputs (RPOSO/RNEGO and RCKO). This loopback connects an internal copy of the analog transmit signal (XTIP and XRING outputs) to the receiver input, so that virtually all of the device circuitry can be tested. While LAL is active, transmit data continues to be transmitted on XTIP and XRING, but RTIP and RRING inputs are ignored. Applying a high on the XOE pin when Local Analog Loopback is active disables the transmitter outputs and causes an RLOS.
2.5.2 Local Digital Loopback
Local Digital Loopback (LDL) causes the transmit data and clock inputs (TPOSI/TNEGI and TCLK) to be looped back to the receiver outputs (RPOSO/RNEGO and RCKO). This loopback includes the JAT (if enabled) but does not include the line transmit and receive circuitry. Consequently, XTIP and XRING transmitter outputs are unaffected, and receiver RTIP and RRING inputs remain connected to the line to monitor for RLOS. Also, the AIS (all 1s) generator is not included in the loopback path so that AIS can be transmitted toward the line while simultaneously providing a local loopback.
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Quad T1/E1 Line Interface
2.0 Circuit Description
2.5 Loopbacks
2.5.3 Remote Line Loopback
Remote Line Loopback (RLL) causes the received data on RTIP/RRING line inputs to be looped back and re-transmitted on XTIP/XRING line outputs. This loopback includes all receive and transmit circuitry and the JAT, but does not include the ZCS decoder and encoder. If the JAT is not enabled, RLL enables the JAT in the transmit direction for the duration of the loopback. In this case, the JAT elastic store size is 8 bits. The receiver outputs (RPOSO/RNEGO and RCKO) continue to output received data; transmit inputs (TPOSI/TNEGI and TCLK) are ignored.
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2.6 Jitter Attenuator
CN8380
Quad T1/E1 Line Interface
2.6 Jitter Attenuator
The jitter attenuator (JAT) attenuates jitter in the receive or transmit path, but not both simultaneously. The JAT path configuration and elastic store depth is controlled by the JDIR and JSEL(2:0) pins in Hardware Mode or by the JEN, JDIR, JCENTER, and JSIZE[2:0] bits in the Jitter Attenuator Configuration register [JAT_CR; addr n0] in Host Mode. The JAT can also be completely disabled. The elastic store is configurable using the JSEL(2:0) pins or the JSIZE[2:0] bits in the JAT_CR register. The elastic store sizes available are 8, 16, 32, 64, and 128 bits. The 32-bit elastic store depth is sufficient to meet jitter tolerance requirements in all cases where the JAT cutoff frequency is 6 Hz or below, and when the selected clock reference is frequency-locked. The larger elastic store depths allow greater accumulated phase offsets. For example, the 128-bit depth can tolerate up to 64 bits of accumulated phase offset. Because the elastic store is a fixed size, it can overflow and under-run. If either of these conditions occurs, a Jitter Attenuator Elastic Store Limit Error (JATERR) is reported. In Hardware Mode, JATERR[n] pins are provided, and in Host Mode, the JERR bit in the Interrupt Status Register [ISR; addr n6] is set. The elastic store is a circular buffer with independent read and write pointers. These pointers can be initialized manually using JCENTER in the JAT_CR register. JCENTER resets the write pointer and forces the elastic store read pointer to one half of the programmed JSIZE. Centering is automatic as a result of a JATERR condition, so manually centering is not required. The dejittered receiver recovered clock is output on the RCKO[n] pin if the JAT is configured in the receive path. The receiver input clock and data jitter tolerance and jitter transfer meet TR 62411-1990. Figures 2-8 and 2-9 illustrate jitter tolerance and JAT transfer characteristics.
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CN8380
Quad T1/E1 Line Interface
Figure 2-8. Receiver Input Jitter Tolerance
2.0 Circuit Description
2.6 Jitter Attenuator
10000
Sine Wave Jitter Amplitude (UI pk-pk) [Log Scale]
Typical Receiver Tolerance with JAT Disabled
1000
Typical Receiver Tolerance with Various JAT Sizes Selected
138 UI
100
TR 62411 (T1) Minimum Tolerance
128 bits 64 bits
28 UI
32 bits 16 bits
10
G.824 (T1) Minimum Tolerance Rec. G.823 (E1) Minimum Tolerance
5 UI 1.5 UI
8 bits
1
0.4 UI 0.2 UI 0.1 UI
0.1 0.1
8380_013
1
10
100
1000
10000
100000
Sine Wave Jitter Frequency (Hz) [Log Scale]
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2.6 Jitter Attenuator
CN8380
Quad T1/E1 Line Interface
Figure 2-9. Typical JAT Transfer Characteristics with Various JAT Sizes
0
-10 Rec G.735 (Min. Atten Boundary) -20
Jitter Attenuation (dB)
-30 PUB 62411 (Min. Atten. Boundary) -40
-50
PUB 62411 (Max. Atten. Boundary) JAT Size = 128 64 32 16 8
-60 1 10 100 1000 10000 100000
0_014
Sine Wave Jitter Frequency (Hz) [Log Scale]
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Quad T1/E1 Line Interface
2.0 Circuit Description
2.7 Clock Rate Adapter
2.7 Clock Rate Adapter
The CLAD uses an input clock reference at a particular frequency (8 kHz to 16,384 kHz) to synthesize output clocks at a different frequency (8 kHz to 16,384 kHz). The CLAD outputs are frequency-locked to the selected timing reference. The CLAD can operate with input reference frequencies at multiples and submultiples of T1 or E1 line rates. The CLAD block diagram is illustrated in Figure 2-10.
Figure 2-10. CLAD Block Diagram
Clock Rate Adapter (CLAD)
CLADI RCKO[1] RCKO[2] RCKO[3] RCKO[4] / [RSCALE] Factor CLADR Phase Detector Loop Filter [LFGAIN] NCO [FREE] 10 MHz Clock Monitor [CMUX]
[G_T1/E1N] [CPD_IE]
CLAD Control/ Status
[CPDERR] [CPD_INT]
REFCKI
/ [VSCALE] Factor Device I/O Pin Labels in brackets [ ] refer to register bits. CLADV [VSEL] Divider Chain 13
32.768 MHz 2.048 MHz 1.544 MHz
CLK32 CLK2048 CLK1544
Refer to the following registers: Global Configuration; addr 01 CLAD Configuration; addr 02 CLAD Frequency Select; addr 03 CLAD Phase Detector Scale Factor; addr 04 CLAD Status; addr 06
[OSEL]
CLADO [CLK_OE]
8380_015
14
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2.0 Circuit Description
2.7 Clock Rate Adapter
CN8380
Quad T1/E1 Line Interface
2.7.1 Inputs
In Hardware Mode, the CLAD input timing reference is normally taken from a line rate (1,544 kHz--T1 or 2,048 kHz--E1) clock on the CLADI pin. The line rate is determined globally for all channels by settings on the PTS(2:0) pins. The CLAD can be set in free-run mode by removing the clock from CLADI (pull high or low). If clock edges are not present on CLADI, an internal clock monitor automatically switches the timing reference to use the 10 MHz, REFCKI reference. When clock edges are sensed on CLADI, the reference is switched back to CLADI. In Host Mode, the CLAD input timing reference can be selected from six sources. The source can be the received recovered clock (or jitter attenuated clock) output (RCKO[n]) from any of the four channels, the CLADI input pin, or the 10 MHz, REFCKI input (free-run mode). The CLAD reference is configured by writing to the CMUX[2:0] bits in the Global Control Register [GCR; addr 01]. Free-run mode is selected by writing 1 to the FREE bit in the CLAD Configuration Register [CLAD_CR; addr 02].
2.7.2 Outputs
Four CLAD output pins are provided: CLADO, CLK32, CLK1544, and CLK2048. In Hardware Mode, the CLADO output provides only a fixed 8 kHz clock. In Host Mode, the CLADO frequency is programmable. Table 2-10 lists the CLAD outputs and frequencies. For pin definitions, refer to Table 1-1 .
Table 2-10. CLAD Outputs and Frequencies CLAD Output
CLADO
Frequency
Host Mode--Programmable to various frequencies in the range of 8 kHz to 32,768 kHz. Hardware Mode--Fixed 8 kHz. Fixed 32,768 kHz Fixed 1,544 kHz Fixed 2,048 kHz
CLK32 CLK1544 CLK2048
2.7.3 Configuration Options
CLAD modes are selected using the CLAD Configuration Register [CLAD_CR; addr 02]; the CLAD Frequency Select [CSEL; addr 03]; and the CLAD Phase Detector Scale Factor [CPHASE; addr 04]. The CLAD reference can be any of 41 possible frequencies, as listed in Table 2-11.
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CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.7 Clock Rate Adapter
Table 2-11. CLAD Reference Frequencies and Configuration Examples (1 of 2) CLAD Reference (kHz)
8 16 32 64 128 256 512 1024 2048 4096 8192 16,384 32,768
RSCALE
Phase Compare Frequency (kHz)
8 16 32 64 128 256 512 1024 2048 4096 8192 16,384 32,768
VSCALE
CLADV (kHz)
1024 1024 1024 1024 1024 1024 1024 1024 2048 4096 8192 16,384 32,768
VSEL
000 000 000 000 000 000 000 000 000 000 000 000 000
111 110 101 100 011 010 001 000 000 000 000 000 000
0001 0001 0001 0001 0001 0001 0001 0001 0010 0011 0100 0101 0110
12.0625 24.125 48.25 96.5 193 386 772 1544 3088 6176 12,352 24,704
000 000 000 000 000 000 000 000 000 000 000 000
12.0625 24.125 48.25 96.5 193 386 772 1544 3088 6176 12,352 24,704
111 110 101 100 011 010 001 000 000 000 000 000
1544 1544 1544 1544 1544 1544 1544 1544 3088 6176 12,352 24,704
0111 0111 0111 0111 0111 0111 0111 0111 1000 1001 1010 1011
12 24 48 96 192
000 000 000 000 000
12 24 48 96 192
111 110 101 100 011
1536 1536 1536 1536 1536
1101 1101 1101 1101 1101
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2.0 Circuit Description
2.7 Clock Rate Adapter
CN8380
Quad T1/E1 Line Interface
Table 2-11. CLAD Reference Frequencies and Configuration Examples (2 of 2) CLAD Reference (kHz)
384 768 1536
RSCALE
Phase Compare Frequency (kHz)
384 768 1536
VSCALE
CLADV (kHz)
1536 1536 1536
VSEL
000 000 000
010 001 000
1101 1101 1101
20 40 80 160 320 640 1280 2560
000 000 000 000 000 000 000 000
20 40 80 160 320 640 1280 2560
111 110 101 100 011 010 001 000
2560 2560 2560 2560 2560 2560 2560 2560
1100 1100 1100 1100 1100 1100 1100 1100
To configure the CLAD: Choose a CLADO output frequency. Refer to the CLAD Frequency Select register [CSEL; addr 03] for a list of all possible CLADO output frequencies. 2. Configure OSEL to select the CLADO output frequency. 3. Select the desired CLAD timing reference frequency from Table 2-11. 4. Configure RSCALE, VSCALE, VSEL from Table 2-11.
1.
Many RSCALE and VSCALE values other than those shown in Table 2-11 are applicable. For instance, an alternate configuration for an input reference frequency of 2048 kHz is displayed in Table 2-12.
Table 2-12. Sample Alternate Configuration CLAD Reference (kHz)
2048
RSCALE
Phase Compare Frequency (kHz)
1024
VSCALE
CLADV (kHz)
8192
VSEL
001
011
0100
RSCALE is a programmable frequency divider which scales the CLAD reference clock frequency before it is applied to the CLAD's phase detector. Similarly, VSCALE scales the CLAD's internal feedback clock, CLADV These . two clocks must have the same frequency at the phase detector's inputs for the CLAD's loop to properly lock. So the rule is: (CLAD reference freq.) / (RSCALE factor) = (CLADV freq.) / (VSCALE factor)
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CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.8 Test Access Port (JTAG)
2.8 Test Access Port (JTAG)
The CN8380 incorporates printed circuit board testability circuits in compliance with IEEE Std P1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture, commonly known as JTAG (Joint Test Action Group). The JTAG includes a test access port (TAP) and several data registers. The TAP provides a standard interface through which instructions and test data are communicated. A Boundary Scan Description Language (BSDL) file for the CN8380 is available from the factory upon request. The test access port consists of the TRST, TDI, TCK, TMS, and TDO pins. An internal power on reset circuit or the TRST resets the JTAG port.
2.8.1 Instructions
In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST instructions, IDCODE instruction is supported. There are also two private instructions. Table 2-13 lists the JTAG instructions and their codes.
Table 2-13. JTAG Instructions Instructions
BYPASS SAMPLE/PRELOAD EXTEST IDCODE
Code
1111 0001 0000 0010
2.8.2 Device Identification Register
The JTAG ID register consists of a 4-bit version, a 16-bit part number, and an 11-bit manufacturer number as listed in Table 2-14.
Table 2-14. Device Identification JTAG Register Version
0 0 0x0 4 Bits 0 0 1 0 0 0 0 0
Part Number
1 11 0x8380 16 Bits 0 0 0 0 0 0 0 0 0 0 1
Manufacturer ID
1 0 0x0D6 11 Bits 1 0 1 1 0 1
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2.0 Circuit Description
2.8 Test Access Port (JTAG)
CN8380
Quad T1/E1 Line Interface
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3
3.0 Registers
3.1 Address Map
The address map in Table 3-1 lists the three types of registers: * Global Control and Status Registers * Per Channel Registers * Transmitter Shape Registers
Table 3-1. Address Map (1 of 2) Address (Hex) Acronym R/W Description Default Setting(1) (Hex)
Global Control and Status Registers
00 01 02 03 04 06 DID GCR CLAD_CR CSEL CPHASE CSTAT R R/W R/W R/W R/W R Device Identification Global Configuration CLAD Configuration CLAD Frequency Select CLAD Phase Detector Scale Factor CLAD Status
(2)
00 00 00 00 --
Per Channel Registers (n = channel number: 1-4)
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 JAT_CR RLIU_CR TLIU_CR LIU_CTL UNUSED ALARM ISR IER SHAPE0 SHAPE1 R/W R/W R/W R/W -- R R R/W R/W R/W Jitter Attenuator Configuration Receiver Configuration Transmitter Configuration Line Interface Unit Control -- Alarm Status Interrupt Status Register Interrupt Enable Register Transmit Pulse Shape Configuration Transmit Pulse Shape Configuration 00 00 00 00 -- -- 00 00 00 00
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3.0 Registers
3.1 Address Map
CN8380
Quad T1/E1 Line Interface
Table 3-1. Address Map (2 of 2) Address (Hex)
nA nB nC nD nE nF
Acronym
SHAPE2 SHAPE3 SHAPE4 SHAPE5 SHAPE6 SHAPE7
R/W
R/W R/W R/W R/W R/W R/W
Description
Transmit Pulse Shape Configuration Transmit Pulse Shape Configuration Transmit Pulse Shape Configuration Transmit Pulse Shape Configuration Transmit Pulse Shape Configuration Transmit Pulse Shape Configuration
Default Setting(1) (Hex)
00 00 00 00 00 00
Reserved Registers
05 07 08 09 0A 0B 0C 0D 0E 0F 50 51 52-7F CTEST FREG TESTA1 TESTA2 FUSE_CH1 FUSE_CH2 FUSE_CH3 FUSE_CH4 FUSE_RES TESTD TESTA3 TESTA4 RESERVED R/W R/W R/W R/W R R R R R R/W R/W R/W (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) Reserved 00 00 00 00 -- -- -- -- -- 00 00 00 --
Note(s): (1) Registers shown with a default setting are reset to the indicated value during internal power on reset, software RESET, or hardware reset (RESET pin). (2) Value depends on the current device revision. Consult factory.
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CN8380
Quad T1/E1 Line Interface
3.0 Registers
3.2 Global Control and Status Registers
3.2 Global Control and Status Registers
00--Device Identification (DID)
R
7 DID[7] 6 DID[6] 5 DID[5] 4 DID[4] 3 DID[3] 2 DID[2] 1 DID[1] 0 DID[0]
DID[7:4] DID[3:0]
Device ID Device Revision
01--Global Configuration (GCR)
R/W
7 RESET 6 G_T1/E1N 5 CLK_OE 4 CPD_IE 3 TCLK_I/O 2 CMUX[2] 1 CMUX[1] 0 CMUX[0]
RESET
Global Reset--When written to 1, initiates an internal global reset process which sets all configuration registers to their default values for all four ports. Also, several output pins are three-stated. After RESET is complete, the following is true: * Digital receiver outputs (RPOSO[1:4], RNEGO[1:4], RCKO[1:4]) are three-stated. * Transmitter line outputs (XTIP[1:4], XRING[1:4]) are three-stated. * CLK1544, CLK2048, and CLADO clock outputs are three-stated. * Transmitter clocks, TCLK[1:4] are configured as inputs. * All interrupt sources are disabled. * All configuration registers are set to default values. Global Clock Mode--This bit selects one of two CLAD operating modes. The CLAD can operate in a mode which insures the minimum output jitter on the CLK1544 output or the CLK 2048 output. 0 = CLK2048 output jitter minimized 1 = CLK1544 output jitter minimized Clock Output Enable--Determines output state of CLK1544, CLK2048, and CLADO clock outputs. 0 = Clock outputs are three-stated 1 = Clock outputs are enabled CLAD Phase Detector Error Interrupt Enable--Enables CLAD loss of lock detector, CPD_INT [CSTAT; addr 06], to generate an interrupt request. 0 = Interrupt disabled 1 = Interrupt enabled Transmit Clock Input/Output--Determines whether TCLK[1:4] pins are inputs or outputs. 0 = TCLK[1:4] pins are inputs 1 = TCLK[1:4] pins are outputs
G_T1/E1N
CLK_OE
CPD_IE
TCLK_I/O
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3.0 Registers
3.2 Global Control and Status Registers
CMUX[2:0]
CN8380
Quad T1/E1 Line Interface
CLAD Multiplexer Select--Selects the CLAD reference clock source input to the CLAD phase detector if FREE = 0 [CLAD_CR; addr 02]. The source can be the receive recovered clock output (RCKO) from any of the four channels or the CLAD input pin. 000 = CLADI pin 001 = RCKO[1] from channel #1 010 = RCKO[2] from channel #2 011 = RCKO[3] from channel #3 100 = RCKO[4] from channel #4
02--CLAD Configuration (CLAD_CR)
R/W
7 FREE 6 RSCALE[2] 5 RSCALE[1] 4 RSCALE[0] 3 LFGAIN[3] 2 LFGAIN[2] 1 LFGAIN[1] 0 LFGAIN[0]
FREE
Free-Run CLAD--Disables the CLAD phase detector in the CLAD, which forces the numerically controlled oscillator (NCO) to free-run based on the 10 MHz REFCKI input clock accuracy. 0 = normal (closed loop) CLAD operation 1 = free run (open loop) NCO operation CLAD Reference Scale Factor--Divides CLAD reference signal by 2 [RSCALE] to form CLADR input to the phase detector. Applicable only if FREE is 0. Allows the system to supply CLADI frequency, up to a maximum of 128 times the desired CLADR reference frequency. RSCALE 000 001 010 011 100 101 110 111 Scale Factor
1 2 4 8 16 32 64 128
RSCALE[2:0]
CLADR Reference CLADR = CLADI CLADR = CLADI/2 CLADR = CLADI/4 CLADR = CLADI/8 CLADR = CLADI/16 CLADR = CLADI/32 CLADR = CLADI/64 CLADR = CLADI/128
LFGAIN[3:0]
Loop Filter Gain-- Selects the NCO loop filter's proportional phase error gain. Lower gain values reduce phase response time, and higher gain values increase phase response time. Note that loop instability or acquisition failures may result from incorrectly programmed LFGAIN values. LFGAIN 0000 | 1111 Proportional Gain 1/20 | 1/215
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Quad T1/E1 Line Interface
3.0 Registers
3.2 Global Control and Status Registers
03--CLAD Frequency Select (CSEL)
R/W
7 VSEL[3] 6 VSEL[2] 5 VSEL[1] 4 VSEL[0] 3 OSEL[3] 2 OSEL[2] 1 OSEL[1] 0 OSEL[0]
VSEL[3:0]
CLADV Frequency Select--Applicable only if FREE [CLAD_CR; addr 02] is 0. Picks one of 13 CLAD divider chain frequencies to feed back to the phase detector. The selected CLADV frequency passes to VSCALE for further division before phase detector comparison. Setting VSEL to invalid values is undefined. VSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLADV Frequency (kHz)
1024 2048 4096 8192 16,384 32,768 1544 3088 6176 12,352 24,704 2560 1536
1 x E1 2 x E1 4 x E1 8 x E1 16 x E1 1 x T1 2 x T1 4 x T1 8 x T1 16 x T1 1 x T1 (unframed)
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3.0 Registers
3.2 Global Control and Status Registers
OSEL[3:0]
CN8380
Quad T1/E1 Line Interface
CLADO Frequency Select--Picks one of 14 CLAD divider chain frequencies to output on the CLADO pin. OSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLADO Frequency (kHz)
8 1024 2048 4096 8192 16,384 32,768 1544 3088 6176 12,352 24,704 2560 1536
1 x E1 2 x E1 4 x E1 8 x E1 16 x E1 1 x T1 2 x T1 4 x T1 8 x T1 16 x T1 1 x T1(unframed)
04--CLAD Phase Detector Scale Factor (CPHASE)
R/W
7 -- 6 -- 5 -- 4 -- 3 -- 2 VSCALE[2] 1 VSCALE[1] 0 VSCALE[0]
VSCALE[2:0]
CLAD Variable Scale Factor--Divides CLADV signal by 2 [VSCALE] before use in the phase detector. Applicable only if FREE [CLAD_CR; addr 02] is 0. Allows the system to select CLADV frequency that is up to 128 times CLADR. VSCALE 000 001 010 011 100 101 110 111 Scale Factor 1 2 4 8 16 32 64 128 Phase Detector Variable Input CLADV selected by VSEL [addr 03] CLADV/2 CLADV/4 CLADV/8 CLADV/16 CLADV/32 CLADV/64 CLADV/128
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Quad T1/E1 Line Interface
3.0 Registers
3.2 Global Control and Status Registers
05--CLAD Test (CTEST)
R/W
7 CTEST[7] 6 CTEST[6] 5 CTEST[5] 4 CTEST[4] 3 CTEST[3] 2 CTEST[2] 1 CTEST[1] 0 CTEST[0
Factory use only. Must be remain at default value, 00.
06--CLAD Status (CSTAT)
R
7 6 5 4 CPDERR 3 2 1 0 CPD_INT
--
CPDERR
--
--
--
--
--
CLAD Phase Detector Error--Real-time indicator of the CLAD phase detector status. CPDERR indicates when the CLADO loses lock with respect to the selected CLADI reference clock. 0 = CLAD Phase Detector is in lock 1 = CLAD Phase Detector is out of lock CLAD Phase Detector Error Interrupt--Indicates a change in status of CPDERR. CPD_INT is latched high upon a change in status of CPDERR and held until read clear.
CPD_INT
07--(FREG)
R/W
7 F_OP[1] 6 F_OP[0] 5 4 F_ADDR[4] 3 F_ADDR[3] 2 F_ADDR[2] 1 F_ADDR[1] 0 F_ADDR[0]
--
Factory use only. Must be remain at default value, 00.
08--(TESTA1)
R/W
7 A_TEST[7] 6 A_TEST[6] 5 A_TEST[5] 4 A_TEST[4] 3 A_TEST[3] 2 A_TEST[2] 1 A_TEST[1] 0 A_TEST[0]
Factory use only. Must be remain at default value, 00.
09--(TESTA2)
R/W
7 A_TEST[15] 6 A_TEST[14] 5 A_TEST[13] 4 A_TEST[12] 3 A_TEST[11] 2 A_TEST[10] 1 A_TEST[9] 0 A_TEST[8]
Factory use only. Must be remain at default value, 00.
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3.0 Registers
3.2 Global Control and Status Registers
CN8380
Quad T1/E1 Line Interface
0A--(FUSE_CH1)
R/W
7 F_TR[5] 6 5 4 F_TR[4] 3 F_TR[3] 2 F_TR[2] 1 F_TR[1] 0 F_TR[0]
--
--
Factory use only. Must be remain at default value, 00.
0B--(FUSE_CH2)
R/W
7 6 5 4 F_TR[10] 3 F_TR[9] 2 F_TR[8] 1 F_TR[7] 0 F_TR[6]
--
--
--
Factory use only. Must be remain at default value, 00.
0C--(FUSE_CH3)
R/W
7 6 5 4 F_TR[15] 3 F_TR[14] 2 F_TR[13] 1 F_TR[12] 0 F_TR[11]
--
--
--
Factory use only. Must be remain at default value, 00.
0D--(FUSE_CH4)
R/W
7 6 5 4 F_TR[20] 3 F_TR[19] 2 F_TR[18] 1 F_TR[17] 0 F_TR[16]
--
--
--
Factory use only. Must be remain at default value, 00.
0E--(FUSE_RES)
R/W
7 PREVIEW 6 5 F_TR[26] 4 F_TR[25] 3 F_TR[24] 2 F_TR[23] 1 F_TR[22] 0 F_TR[21]
--
Factory use only. Must be remain at default value, 00.
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CN8380
Quad T1/E1 Line Interface
3.0 Registers
3.2 Global Control and Status Registers
0F--(TESTD)
R/W
7 D_CTL[2] 6 D_CTL[1] 5 D_CTL[0] 4 D_CH[1] 3 D_CH[0] 2 D_MD[2] 1 D_MD[1] 0 D_MD[0]
Factory use only. Must be remain at default value, 00.
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3.0 Registers
3.3 Per Channel Registers
CN8380
Quad T1/E1 Line Interface
3.3 Per Channel Registers
10, 20, 30, 40--Jitter Attenuator Configuration (JAT_CR)
R/W
7 T1/E1 6 5 JEN 4 JDIR 3 JCENTER 2 JSIZE[2] 1 JSIZE[1] 0 JSIZE[0]
--
T1/E1
T1/E1 Select--Enables receive and transmit circuits to operate at either the T1 or E1 line rate. All configuration register settings should be re-initialized after changing the T1/E1 control bit. T1/E1 selects the nominal line rate (shown below), while the exact receive and transmit line rate frequencies are independently determined by their respective input clock or data references. The actual receive and transmit line frequency can vary within defined tolerances. 0 = 2.048 MHz line rate (E1) 1 = 1.544 MHz line rate (T1) Jitter Attenuator Enable--JEN enables the JAT in the receive or the transmit path (determined by JDIR bit). 0 = Disable JAT 1 = Enable JAT Select JAT Path--Applicable only when the JAT is enabled (see JEN description). JAT elastic store is placed in either the receive or transmit path. 0 = JAT in TX path 1 = JAT in RX direction, jitter attenuated recovered clock output on RCKO Force JAT to Center--Writing a 1 to JCENTER resets the elastic store write pointer and forces the elastic store read pointer to one-half the programmed JSIZE. JCENTER is typically written at power-up. JCENTER can optionally be asserted after recovery from a loss of signal (RLOS or RALOS) or in response to a transmit loss of clock (TLOC), or after recovering from a persistent JAT elastic store error (JERR). The JCENTER bit is self clearing. 0 = normal operation 1 = recenter JAT elastic store JAT Elastic Store Size--Selects the maximum depth of the JAT elastic store. The 32-bit depth is sufficient to meet jitter attenuation requirements in all cases where the JAT cutoff frequency is programmed at 6 Hz. However, in cases where an external reference is selected or a narrow loop bandwidth is programmed, the elastic store depth can tolerate up to 64 UI (128 bits) of accumulated phase offset. JSIZE 000 001 010 011 1xx Elastic Store Size 8 Bits 16 Bits 32 Bits 64 Bits 128 Bits
JEN
JDIR
JCENTER
JSIZE[2:0]
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Quad T1/E1 Line Interface
3.0 Registers
3.3 Per Channel Registers
11, 21, 31, 41--Receiver Configuration (RLIU_CR)
R/W
7 UNIPOLAR 6 ZCS 5 CLK_POL 4 RAWMD 3 EQ_DIS 2 ATTN 1 0 SQUELCH
--
UNIPOLAR
Unipolar Mode--Selects between unipolar and bipolar modes for digital transmit and receive signals. In unipolar mode, RPOSO/RNEGO signals are replaced by RDATO/BPV signals. AMI encoded received data is decoded and output on RDATO in unipolar, NRZ format; and BPV indicates that the currently received bit is a bipolar violation. TPOSI is replaced with TDATI and accepts unipolar, NRZ formatted transmit data. TNEGI is not used in this mode. In unipolar mode, ZCS can replace AMI encoding. Refer to the ZCS bit description below. In bipolar mode, RPOSO/RNEGO signals output received data in bipolar dual-rail format, where a high level on RPOSO indicates receipt of a positive AMI pulse, and a high level on RNEGO indicates receipt of a negative AMI pulse on RTIP/RING inputs. TPOSI/TNEGI inputs accept bipolar dual-rail transmit data, where a high on TPOSI causes a positive output pulse on XTIP/XRING, and a high on TNEGI causes a negative output pulse. 0 = Digital transmit/receive signals are bipolar, dual-rail 1 = Digital transmit/receive signals are unipolar, NRZ Zero Code Suppression Enable--Enables HDB3 or B8ZS zero code suppression encoding/decoding on digital transmit and receive signals and is only applicable if unipolar mode is selected. In T1 mode (T1/E1 = 1) [addr n0], B8ZS encoding/decoding is selected. In E1 mode (T1/E1 = 0), HDB3 encoding/decoding is selected. In the transmit direction, the ZCS encoder replaces sequences of eight or four 0s with a recoverable code. In the receive direction, the ZCS decoder replaces received codes with eight 0s in T1 mode, or four 0s in E1 mode. The B8ZS code is 000VB0VB and the HDB3 code is X00V; where B is a normal AMI pulse, V is a bipolar violation, and X is a "don't-care." These are standard T1 and E1 line code options. 0 = ZCS encode/decode disabled 1 = ZCS encode/decode enabled Clock Polarity--Selects the digital receive data clocking edge. Normally, RPOSO/RNEGO is output on the rising edge of RCKO. If CLK_POL is set to 1, RPOSO/RNEGO is output on the falling edge of RCKO. 0 = Data out on rising RCKO 1 = Data out on falling RCKO Raw Receive Mode--RPOSO/RNEGO data outputs are replaced by the data slicer output, and RCKO is replaced by the logical OR of RPOSO/RNEGO. A high on RPOSO indicates a positive pulse, and a high on RNEGO indicates a negative pulse on RTIP/RRING line inputs. 0 = Normal receiver output 1 = Slicer data output enabled Equalizer Disable--Disables the receiver equalizer. (Test mode only) 0 = Equalizer enabled 1 = Equalizer disabled Bridge Attenuation--Compensates for 20 dB resistive signal attenuation caused by placement of bridge resistors in series with the normal receive termination resistance. Also, in this mode a lower threshold for RALOS is selected to compensate for the 20 db attenuation. 0 = Normal receiver input levels 1 = 20 dB compensation enabled
ZCS
CLK_POL
RAWMD
EQ_DIS
ATTN
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3.0 Registers
3.3 Per Channel Registers
CN8380
Quad T1/E1 Line Interface
SQUELCH
Enable Receive Signal Squelch--The digital receiver outputs, RPOSO/RNEGO, are forced to zero when RALOS is declared. SQUELCH is useful in attached framer applications to allow the framer to detect LOS during an RALOS condition. 0 = Normal 1 = Squelch RPOSO/RNEGO outputs upon RALOS detect
12, 22, 32, 42 --Transmitter Configuration (TLIU_CR)
R/W
7 ALT_TR 6 TERM 5 PDN 4 T_BOOST 3 PPT 2 PULSE[2] 1 PULSE[1] 0 PULSE[0]
ALT_TR
Alternate Transformer Select--Adjusts the transmit output level for one of two possible transmitter transformer turns ratios. Normally, a turns ratio of 1:2 for the transmitter is used. An alternate transformer with turns ratio of 1:1.36 can be selected to minimize power dissipation 0 = Normal transformer (1:2) 1 = Alternate transformer (1:1.36) Transmitter Termination Select--Adjusts the transmit XTIP/XRING output amplitude to compensate for the presence of an optional external termination resistor. The external resistor is placed in parallel across XTIP/XRING on systems that must meet transmitter return loss requirements. Refer to Figure 2-7, Transmit Termination Components, for resistor placement. Refer to Tables 2-4 through 2-8 for return loss values. 0 = no external transmit termination resistor used 1 = external transmit termination resistor used Power Down--Unused channels can be put into a low power mode in order to minimize power dissipation. In low power mode, XTIP/XRING, RPOSO/RNEGO, and RCKO outputs are three-stated. All other receiver functions are not affected. 0 = Channel is disabled, low power mode 1 = Channel is enabled, normal operation Transmit Level Boost--Adjusts the transmit output level to compensate for series resistance added to the output by surge protection circuitry. Typical resistance values are 5.6 ohms in series with line side XTIP and XRING signals. 0 = No compensation 1 = Compensation enabled Programmed Pulse Template--Enables custom transmit pulse transmission. The programmed pulse shape stored in the corresponding shape register, SHAPEn [addr n8 - nF], is used for transmission. 0 = Pulse template selected by PULSE(2:0) 1 = Programmed pulse template selected
TERM
PDN
T_BOOST
PPT
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PULSE[2:0]
3.0 Registers
3.3 Per Channel Registers
Transmit Pulse Template Select--Each positive or negative pulse output on XTIP/XRING is shaped to meet the transmit pulse template according to the selected cable length and type. Custom shape programming for alternative cable types or pulse templates can be set using the SHAPE0-SHAPE7 registers [addr n8 - nF]. PULSE 000 001 010 011 100 101 110 111 Cable Length 0-133 ft. 133-266 ft. 266-399 ft. 399-533 ft. 533-655 ft. ITU-T G.703 ITU-T G.703 I.431 ISDN Cable Type 100 Twisted Pair 100 Twisted Pair 100 Twisted Pair 100 Twisted Pair 100 Twisted Pair 75 Coaxial Cable 120 Twisted Pair 100 Twisted Pair Application T1 DSX T1 DSX T1 DSX T1 DSX T1 DSX E1 E1 T1 CSU/NCTE
13, 23, 33, 43--LIU Control (LIU_CTL)
R/W
7 AISCLK 6 AUTO_AIS 5 TAIS 4 LLOOP 3 RLOOP 2 TAIS_PE 1 LLOOP_PE 0 RLOOP_PE
AISCLK
Enable Automatic ACKI Switching--If AISCLK is active, the transmitter clock is automatically switched to reference TACKI (T1) or EACKI (E1) instead of TCLK when transmitting AIS (all 1s) data. Set AISCLK only if the system supplies an alternate line rate clock on the TACKI or EACKI pins. Also refer to description of AUTO_AIS/TAIS below. 0 = TACKI/EACKI is not used to transmit AIS 1 = TACKI/EACKI is used to transmit AIS Automatic Transmit Alarm Indication Signal Manual Transmit Alarm Indication Signal--When activated manually (TAIS) or automatically (AUTO_AIS), the AIS generator replaces all data output on XTIP/XRING with an unframed all-1s signal (AIS). This includes replacing data supplied from TPOSI/TNEGI and from the receiver during Remote Line Loopback. Automatic mode sends AIS for the duration of transmit loss of clock [TLOC; addr n5]. If AISCLK is enabled, the transmit clock is switched to use TACKI or EACKI to transmit AIS.
AUTO_AIS TAIS
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3.3 Per Channel Registers
CN8380
Quad T1/E1 Line Interface
AIS transmission does not affect transmit data that is looped back to the receiver during Local Digital Loopback. This allows Local Digital Loopback to be active simultaneously with the transmission of AIS. If TAIS is activated when RLOOP is enabled, AIS is transmitted using the jitter-attenuated received clock. Refer to the descriptions of RLOOP and LLOOP below. Table 3-2 lists transmitter operating modes resulting from various configuration settings and input conditions.
Table 3-2. Transmitter Operating Modes Configuration and Input Status RLOOP
0 0 0 0 0 0 1 1 Note:
Transmitter Mode AISCLK
X 0 1 X 0 1 X X
TLOC
X X X 0 1 1 X X
TAIS
0 1 1 0 0 0 0 1
AUTO_AIS
0 X X 1 1 1 X X
Transmit Data
Tx Data AIS AIS Tx Data AIS AIS Rx Data AIS
Transmit Clock
TCLK TCLK TACKI/EACKI TCLK TCLK TACKI/EACKI RCLK RCLK
X is don't-care.
LLOOP
Local Analog Loopback--Bipolar data from XTIP/XRING is internally connected to RTIP/RRING inputs. Externally applied data on RTIP/RRING inputs is ignored. XTIP/XRING output data is unaffected. Asserting both LLOOP and RLOOP activates Local Digital Loopback. Refer to the RLOOP description below. Remote Line Loopback--Dual-rail bipolar data from the receiver (or receive JAT) is internally connected to the transmitter (or transmit JAT). The recovered clock from the RPLL (or JCLK) is also looped to provide the transmit clock. Loopback data retains BPV transparency. Received data is allowed to pass to the RZCS decoder, and digital outputs are unaffected. Asserting both LLOOP and RLOOP activates LDL. Dual-rail bipolar data from the TZCS encoder (or transmit jitter attenuator) is internally connected to the RZCS decoder (or receive jitter attenuator) inputs. The transmit clock, TCLK, is also looped to provide the receive clock, RCKO. Externally applied data on RTIP/RRING inputs are blocked; however, RLOS and RALOS detect circuitry continues to operate and report receive signal status. XTIP/XRING output data is unaffected. LLOOP 0 0 1 1 RLOOP 0 1 0 1 Loopback No loopback Remote Line Loopback Local Analog Loopback Local Digital Loopback
RLOOP
TAIS_PE
TAIS Pin Enable--Allows the use of the TAIS hardware pin instead of the TAIS register bit to manually transmit AIS. 0 = Use TAIS register bit 1 = Use TAIS pin
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3.0 Registers
3.3 Per Channel Registers
LLOOP_PE
LLOOP Pin Enable--Allows the use of the LLOOP hardware pin instead of the LLOOP register bit to control loopbacks. 0 = Use LLOOP register bit 1 = Use LLOOP pin RLOOP Pin Enable--Allows the use of the RLOOP hardware pin instead of the RLOOP register bit to control loopbacks. 0 = Use RLOOP register bit 1 = Use RLOOP pin
RLOOP_PE
15, 25, 35, 45--Alarm Status (ALARM)
R
7 RALOS 6 RLOS 5 TLOC 4 TLOS 3 TSHORT 2 JERR 1 BPV 0
--
RALOS RLOS TLOC TLOS TSHORT JERR BPV
Receive Analog Loss of Signal Detect--Indicates receiver analog loss of signal. Receive Loss of Signal Detect--Indicates receiver loss of signal. Transmit Loss of Clock Detect--Indicates loss of transmit clock, TCLK. Transmit Loss of Signal Detect--Indicates a transmitter signal fault detected by the DPM. Transmit Short Circuit Detect--Indicates transmitter output overload. Jitter Attenuator Error Detect--Indicates jitter attenuator FIFO overflow or underrun. Bipolar Violation Detect--Indicates a bipolar violation error. If ZCS encoding/decoding is enabled, BPV is asserted only for bipolar violations which are not part of the ZCS code.
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3.0 Registers
3.3 Per Channel Registers
CN8380
Quad T1/E1 Line Interface
16, 26, 36, 46--Interrupt Status Register (ISR)
An Interrupt Status register (ISR) bit is latched active (high) whenever its corresponding interrupt source [ALARM; addr n5] reports an interrupt event. All latched ISR bits are cleared when ISR is read. If the corresponding interrupt enable [IER; addr n7] is active (high), each interrupt event forces the IRQ output pin active (low). ISR reports an interrupt event when an alarm status [ALARM; addr n5] changes from inactive to active (rising edge) or from active to inactive (falling edge). The associated real-time alarm status must be read to determine the current alarm state.
R
7 RALOS 6 RLOS 5 TLOC 4 TLOS 3 TSHORT 2 JERR 1 BPV 0
--
RALOS RLOS TLOC TLOS TSHORT JERR BPV
Receive Analog Loss of Signal--Indicates receiver analog loss of signal status change. Receive Loss of Signal--Indicates receiver loss of signal status change. Transmit Loss of Clock--Indicates transmitter loss of clock status change. Transmit Loss of Signal--Indicates transmitter output signal fault status change. Transmit Short Circuit--Indicates transmitter loss of analog signal status change. Jitter Attenuator Error-- Indicates JAT FIFO empty/full status change. Bipolar Violation-- Indicates a non-zero code bipolar violation status change.
17, 27, 37, 47--Interrupt Enable Register (IER)
R/W
7 RALOS 6 RLOS 5 TLOC 4 TLOS 3 TSHORT 2 JERR 1 BPV 0
--
RALOS RLOS TLOC TLOS TSHORT JERR BPV
Enables Receive Analog Loss Of Signal Enables Receive Loss Of Signal Enables Transmit Loss Of Clock Enables Transmit Loss Of Signal Enables Transmit Short Circuit Enables Jitter Attenuator Error Enables Bipolar Violation
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Quad T1/E1 Line Interface
3.0 Registers
3.4 Transmitter Shape Registers
3.4 Transmitter Shape Registers
The following SHAPE registers allow custom programming of the transmit signal pulse shapes. Each set of eight registers determines the shape for its corresponding channel. A channel [n] is configured to use custom shapes by first programming the eight SHAPE[n] registers, then setting register bit PPT [addr n1]. For more information on transmitter functionality, refer to Section 2.4, Transmitter.
18 - 1F--Transmit PULSE Shape CONFIGURATION (SHAPE1)
R/W
7 6 5 4 SHAPE[4] 3 SHAPE[3] 2 SHAPE[2] 1 SHAPE[1] 0 SHAPE[0]
--
--
--
28 - 2F--Transmit PULSE Shape CONFIGURATION (SHAPE2)
R/W
7 6 5 4 SHAPE[4] 3 SHAPE[3] 2 SHAPE[2] 1 SHAPE[1] 0 SHAPE[0]
--
--
--
38 - 3F--Transmit PULSE Shape CONFIGURATION (SHAPE3)
R/W
7 6 5 4 SHAPE[4] 3 SHAPE[3] 2 SHAPE[2] 1 SHAPE[1] 0 SHAPE[0]
--
--
--
48 - 4F--Transmit PULSE Shape CONFIGURATION (SHAPE4)
R/W
7 6 5 4 SHAPE[4] 3 SHAPE[3] 2 SHAPE[2] 1 SHAPE[1] 0 SHAPE[0]
--
--
--
50--(TESTA3)
R/W
7 A_TEST[23] 6 A_TEST[22] 5 A_TEST[21] 4 A_TEST[20] 3 A_TEST[19] 2 A_TEST[18] 1 A_TEST[17] 0 A_TEST[16]
Factory use only. Must be remain at default value, 00.
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3.0 Registers
3.4 Transmitter Shape Registers
CN8380
Quad T1/E1 Line Interface
51--(TESTA4)
R/W
7 A_TEST[31] 6 A_TEST[30] 5 A_TEST[29] 4 A_TEST[28] 3 A_TEST[17] 2 A_TEST[16] 1 A_TEST[15] 0 A_TEST[14]
Factory use only. Must be remain at default value, 00.
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4
4.0 Electrical/Mechanical Specifications
This chapter contains the following sections: * Absolute Maximum Ratings * Recommended Operating Conditions * DC Characteristics * Performance Characteristics * AC Characteristics * Packaging
4.1 Absolute Maximum Ratings
Table 4-1. Absolute Maximum Ratings Symbol
VDD VDD Vi ESD
Parameter
Power Supply (measured to GND) Voltage Differential (between any 2 VDD pins) Constant Voltage on any Signal Pin Transient Voltage on any Signal Pin HBM rating CDM rating MMM rating Constant Current on any Signal Pin Transient Current on any Signal Pin Digital Pins Analog Pins (TIP, RING) Storage Temperature Junction Temperature: (jA x VDD x IDD) + Tamb Vapor Phase Soldering Temperature (1 minute) Thermal Resistance (128 MQFP), Still Air
Minimum
-0.5
Maximum
5.0 0.5
Units
V V V kV V V mA mA mA
C C C C
-1.0
VDD + 0.5 2 700 200
Ii LATCHUP
-10 -400 -400 -65 -40
+10 +400 +400 150 125 220 36
Ts Tj Tvsol JA
/W
Stresses above those listed here may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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4.2 Recommended Operating Conditions
CN8380
Quad T1/E1 Line Interface
4.2 Recommended Operating Conditions
Table 4-2. Recommended Operating Conditions Symbol
VDD, VAA, VAAT, VAAR, VAACC VGG(1) Tamb Vih(1) Vil
NOTE(S):
Parameter
Supply voltage
Minimum
3.14
Maximum
3.47
Units
V
ESD Rail Ambient operating temperature Input high voltage Input low voltage
3.14
5.25 +85 VGG + 0.5 0.8
V
C
-40
2.0
V V
-0.5
(1) VGG is normally connected to VDD. VGG is connected to + 5 V supply if input signals are 5 V logic.
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Quad T1/E1 Line Interface
4.0 Electrical/Mechanical Specifications
4.3 DC Characteristics
4.3 DC Characteristics
Table 4-3. DC Characteristics Symbol
IDD
Parameter
Supply current (all channels in low power mode, PDN [TLIU_CR; addr n2]) Supply current (50% 1s, all channels enabled, includes transmit load current) Supply current (all 1s, all channels enabled, includes transmit load current)
Minimum
60 -- -- 0.2 -- -- 2.5 -- 2.0 -0.5 40
Typical
-- 200 -- -- 0.5 -- -- -- -- -- 100 1 1 2 2 70 50
Maximum
-- -- 650 -- -- 1.25 -- 1.0 VGG + 0.5 0.8 500 10 10 5 5 85 160
Units
mA mA mA W W W V V V V
PD
Device power dissipation (all channels in low power mode, PDN [TLIU_CR; addr n2]) Device power dissipation (50% 1s, all channels enabled) Device power dissipation (all 1s, all channels enabled)
Voh Vol Vih Vil Ipr Il Ioz Cin Cout Cld Iosc
Output high voltage (Ioh = - 400 A) Output low voltage (Ioh = - 400 A) Input high voltage Input low voltage Resistive pull-up current Input leakage current Three-state leakage current Input capacitance (f = 1 MHz) Output capacitance Capacitive loading (test condition) Short circuit output current (except XTIP/XRING)
A A A
pF pF pF mA
-10 -10
-- -- -- 37
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4.0 Electrical/Mechanical Specifications
4.4 Performance Characteristics
CN8380
Quad T1/E1 Line Interface
4.4 Performance Characteristics
Table 4-4. Performance Characteristics Parameter Minimum Receiver
T1 receiver sensitivity (attenuation @ 772 kHz) E1 receiver sensitivity (attenuation @ 1024 kHz) RTIP[n]. RRING[n] inputs: Input impedance (unterminated) Peak-to-peak voltage (differential) Return loss Receive clock recovery (PLL) Consecutive zeros tolerance before loss of lock T1 frequency lock range E1 frequency lock range Receive noise immunity (SNR) Near-end crosstalk (215 PRBS) 60 Hz longitudinal Gaussian white noise RCKO intrinsic jitter with JAT disabled RCKO intrinsic jitter with JAT enabled +3 +3 -- -- 10 6 TBD
Typical
Maximum
Units
-12 -12
12 10
dB dB
k V dB bits kHz kHz
23
-0.1 -0.4
-- -- -- -- --
75 -- --
100 +0.3 +0.4
15 18 TBD -- --
18 20 TBD 0.125 0.05
dB dB dB UI P-P UI P-P
Transmitter
Transmitter XTIP[n], XRING[n] outputs: Output impedance (XOE = 1, high impedance) Output impedance (XOE = 0, unterminated) Short circuit current into 1 load T1 pulse amplitude, 100 UTP(1) E1 pulse amplitude, 75 coax(1) E1 pulse amplitude, 120 UTP(1) Positive/negative pulse imbalance Return loss Transmitter signal power level (3 kHz band): Power @ 772 kHz Power @ 1544 kHz (relative to power @ 772 kHz) Transmitter output intrinsic jitter with JAT disabled Transmitter output intrinsic jitter with JAT enabled
NOTE(S):
10 -- -- 2.7 2.14 2.7
100 1 2 3.0 2.37 3.0 -- TBD 15
-- -- 50 3.3 2.6 3.3 +10 -- +19 -- 0.125 0.05
k k mA V V V % dB dBm dB UI UI
-10
-- 12
-25
-- --
-36
-- --
(1) These values are measured on the line side of the transformer with an appropriate value load resister in place of a cable.
4-4
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Quad T1/E1 Line Interface
4.0 Electrical/Mechanical Specifications
4.5 AC Characteristics
4.5 AC Characteristics
This section provides details about the following timing features: * XOE * RESET * CLAD * Receiver signals * Transmitter signals * Host serial port * JTAG interface
Table 4-5. XOE Timing Parameters Symbol
1 2
Parameter
XOE[n] high to XTIP[n]/XRING[n] three-state XOE[n] low to XTIP[n]/XRING[n] active
Minimum
Maximum
20 20
Units
ns ns
NOTE(S): See Figure 4-1.
Figure 4-1. XOE Timing Diagram
XOE [n] 1 XTIP[n], XRING[n]
8380_016
2
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4.5 AC Characteristics
CN8380
Quad T1/E1 Line Interface
Table 4-6. RESET Timing Parameters Symbol
1 2 3
NOTE(S):
Parameter
RESET pulse width RESET low to output signals three-state RESET[n] high to output signals active
Minimum
500
Maximum
Units
ns
20 20
ns ns
1. Output signals: RCKO[n], RPOSO[n], RNEGO[n], XTIP[n], XRING[n], CLK1544, CLK2048, CLADO, RLOS[n], JATERR[n], TDO, SDO, IRQ 2. See Figure 4-2.
Figure 4-2. RESET Timing Diagram
1 RESET 2 Output Signals
8380_017
3 Three-State
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Quad T1/E1 Line Interface
Table 4-7. CLAD Timing Parameters Symbol
1 -- 2 3 1 1 1 1 2 3 REFCKI frequency CLADI frequency Duty cycle REFCKI, CLADI Rise/fall time (10% to 90%) REFCKI, CLADI CLADO frequency CLK32 frequency CLK1544 frequency CLK2048 frequency Duty cycle CLADO, CLK32, CLK1544, CLK2048 Rise/fall time CLADO, CLK32, CLK1544, CLK2048
4.0 Electrical/Mechanical Specifications
4.5 AC Characteristics
Parameter
Minimum
9.999 8 40 -- 8
Maximum
10.001 16,384 60 20 16,384
Units
MHz kHz % ns MHz MHz MHz MHz % ns
32.768 (Locked to CLAD reference) 1.544 (Locked to CLAD reference) 2.048 (Locked to CLAD reference) 45 -- 55 20
NOTE(S): See Figure 4-3.
Figure 4-3. CLAD Timing Diagram
1 2 90% 10% 3
8380_018
2
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Quad T1/E1 Line Interface
Table 4-8. Receiver Signals Timing Parameters Symbol
1 2/1 -- 3 RCKO[n] frequency RCKO[n] duty cycle Rise/fall time (10% to 90%) RCKO[n], RPOSO[n], RNEGO[n], RDATO[n], BPV[n] RCKO[n] (rising or falling edge) to data valid
Parameter
Minimum
Maximum
Units
kHz % ns ns
1,544 or 2,048 (Locked to line rate) 45 -- -- 55 20 20
NOTE(S): See Figure 4-4.
Figure 4-4. Receiver Signals Timing Diagram
1
RCKO[n] (CLK_POL = 0)
2 3
RPOSO[n], RNEGO[n], RDATO[n], BPV[n]
RCKO[n] (CLK_POL = 1)
8380_019
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Quad T1/E1 Line Interface
Table 4-9. Transmitter Signals Timing Parameters Symbol
1 2/1 2/1 -- 3 4
4.0 Electrical/Mechanical Specifications
4.5 AC Characteristics
Parameter
TCLK[n] frequency (input or output) TCLK[n] duty cycle (input) TCLK[n] duty cycle (output) Rise/fall time (10% to 90%) TCLK[n], TPOSI[n], TNEGI[n], TDATI[n] Data Input to TCLK[n] falling edge setup time TCLK[n] falling edge to data input hold time
Minimum
1.5 20 45 -- 5 5
Maximum
2.1 80 55 20 -- --
Units
MHz % % ns ns ns
NOTE(S): See Figure 4-5.
Figure 4-5. Transmitter Signals Timing Diagram
1
TCLK[n]
2 3 TPOSI[n], TNEGI[n], TDATI[n] 4
8380_020
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Quad T1/E1 Line Interface
Table 4-10. Host Serial Port Timing Parameters Symbol
1 2, 3 2 3 4 5 6 7 8 9 --
Parameter
CS Setup Before SCLK Rising Edge SCLK Frequency SCLK High Pulse Width SCLK Low Pulse Width SDI to SCLK Rising Edge Setup Time SCLK Rising Edge to SDI Hold Time SCLK Rising Edge to CS Hold Time CS Inactive Cycle Time CS Inactive to SDO Three-State SCLK Falling Edge to SDO Valid Time Rise/Fall Time (10% to 90%) SCLK, SDI, SDO
Minimum
10 -- 50 50 10 5 5 100 100
Maximum
-- 8 -- -- -- -- -- -- -- 50
Units
ns MHz ns ns ns ns ns ns ns ns ns
--
20
NOTE(S): See Figures 4-6 through 4-8.
Figure 4-6. Host Serial Port Timing Diagram
Read Timing CS
SCLK
SDI
R / W A0 1
A1
A2
A3
A4
A5
A6
Address/Control Byte D0 D1 D2 D3 D4 D5 D6 D7
SDO
Register Data Byte
Write Timing CS
SCLK
SDI
R / W A0
0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
Address/Control Byte
Register Data Byte
SDO
8380_021
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Quad T1/E1 Line Interface
Figure 4-7. Host Serial Port Write Timing
4.0 Electrical/Mechanical Specifications
4.5 AC Characteristics
CS
1 2 3 6 7
SCLK
4 5
SDI
0
A0 Address/Command Byte
A1
D5
D6 Write Data Byte
D7
8380_022
Figure 4-8. Host Serial Port Read Timing
CS 1 SCLK 4 SDI 5 2 3 7
1
A0 Address/Command Byte
A1 9 8 D6 D7
SDO
D5
8380_023
Read Data Byte
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4.5 AC Characteristics
CN8380
Quad T1/E1 Line Interface
Table 4-11. JTAG Interface Timing Parameters Symbol
1 2 3 4 5 6 7 8 TCK pulse width high TCK pulse width low TMS, TDI setup to TCK rising edge TMS, TDI hold after TCK high TDO hold after TCK falling edge TDO delay after TCK low TDO enable (Low Z) after TCK falling edge TDO disable (High Z) after TCK low
Parameter
Minimum
80 80 20 20 0 -- 2 --
Maximum
-- -- -- -- -- 50 -- 25
Units
ns ns ns ns ns ns ns ns
NOTE(S): See Figure 4-9.
Figure 4-9. JTAG Interface Timing Diagram
TDO
7 1 TCK
5 6
8
3
4
2
TDI TMS
8380_024
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4.0 Electrical/Mechanical Specifications
4.6 Packaging
4.6 Packaging
Figure 4-10. 128-Pin MQFP Mechanical Drawing
E E1 E2 2.00
PIN 1 REF
2.00
D2 D1 D
D1
PIN 1 REF MARK
e
b S Y M B O L A A1 A2 D D1 D2 E E1 E2 L L1 e b c ALL DIMENSIONS IN MILLIMETERS MIN. 0.25 2.57 NOM. 3.04 0.33 2.71 23.20 REF. 20.0 REF. 18.5 REF 17.20 RE. 14.0 REF 12.5 REF 0.88 1.6 REF 0.50 BSC ------MAX 3.40 2.87
DETAIL A
E1
A
A2
c
0.73
1.03
A1
L
DETAIL A
8380_027
L1
0.13 0.13
0.28 0.23
Ref. 128-PIN MQFP (GP00-D448)
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4.6 Packaging
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Quad T1/E1 Line Interface
4-14
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N8380DSA
A
Appendix A: Applicable Standards
Table A-1. Applicable Standards (1 of 2) Standard
ANSI T1.101-1987 T1.102-1993 T1.403-1995 T1.408-1990 Digital Hierarchy--Timing Synchronization Digital Hierarchy--Electrical Interfaces Network to Customer Installation--DS1 Metallic Interface ISDN Primary Rate--Customer Installation Metallic Interfaces AT&T TR 41449-1986 TR 43801(A)-1985 TR 62411-1990 CB 119 ISDN Primary Rate Interface Specification Digital Channel Bank--Requirements and Objectives Accunet T1.5 Service Description and Interface Specification Compatibility Bulletin Bellcore TR-TSY-000008 Issue 2, 1987 TR-TSY-000009 Issue 1, 1986 TR-NPL-000054 Issue 1, 1989 TR-NWT-000057 Issue 2, 1993 TR-TSY-000170 Issue 2, 1993 TR-TSY-000191 Issue 1, 1986 TR-TSY-000303 Issue 2, 1992 TR-NPL-000320 Issue 1, 1988 TA-TSY-000435 Issue 1, 1987 TR-NWT-000499 Issue 5, 1993 SR-NWT-002343 Issue 1, 1993 Digital Interface Between the SLC 96 Digital Loop Carrier System and a Local Digital Switch Asynchronous Digital Multiplexer Requirements and Objectives High-Capacity Digital Service (HCDS) Interface Generic Requirements Functional Criteria for Digital Loop Carrier Systems Digital Cross-Connect System (DCS) Requirements and Objectives Alarm Indication Signal (AIS) Requirements and Objectives Integrated Digital Loop Carrier (IDLC) System Generic Requirements Fundamental Generic Requirements for Metallic Digital Signal Cross-connect Systems DS1 Automatic Facility Protection Switching (AFPS) Rqts. and Objectives Transport Systems Generic Requirements ISDN Primary Rate Interface Guidelines for Customer Premises Equipment ETSI ETS 300 011 (4/92) ETS 300 233 ISDN Primary Rate User-Network Interface Specification and Test Principles Access Digital Section for ISDN Primary Rate
Title
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Appendix A : Applicable Standards
CN8380
Quad T1/E1 Line Interface
Table A-1. Applicable Standards (2 of 2) Standard
ITU-T Recommendation G.703 (1991) Recommendation G.704 (1991) Recommendation G.706 (1991) Recommendation G.732 Recommendation G.733 Recommendation G.734 Recommendation G.735 Recommendation G.736 Recommendation G.737 Recommendation G.738 Draft Recommendation G.775 Recommendation G.821 Recommendation G.823 (3/93) Recommendation G.824 (3/93) Recommendation I.431 Recommendation K.10 Recommendation K.20 Recommendation M.3604 IEEE Std 1149.1a-1993 FCC Part 68.302 (d) FCC Part 68.308 Physical/Electrical Characteristics of Hierarchical Digital Interfaces Synchronous Frame Structures used at Primary Hierarchical Levels Frame Alignment and CRC Procedures Relating to G.704 Frame Structures Characteristics of Primary PCM Multiplex Equipment at 2048 kbps Characteristics of Primary PCM Multiplex Equipment at 1544 kbps Characteristics of Synchronous Digital Multiplex Equipment at 1544 kbps Characteristics of Primary PCM Multiplex Equipment at 2048 kbps; offering Synchronous Digital Access at 384 kbps and/or 64 kbps Characteristics of Synchronous Digital Multiplex Equipment at 2048 kbps Characteristics of External Access Equipment at 2048 kbps; offering Synchronous Digital Access at 384 kbps and/or 64 kbps Characteristics of Primary PCM Multiplex Equipment at 2048 kbps; offering Synchronous Digital Access at 320 kbps and/or 64 kbps Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection Error Performance Monitoring on International Connections Control of Jitter and Wander in Digital Networks based on 2048 kbps Control of Jitter and Wander in Digital Networks based on 1544 kbps Primary Rate User-Network Interface--Layer 1 Specification Unbalance about Earth of Telecommunication Installations Resistibility of Switching Equipment to Overvoltages and Overcurrents Application of Maintenance Principles to ISDN Primary Rate Access IEEE Standard Test Access Port and Boundary Scan Architecture (JTAG) Environment Simulation Metallic Voltage Surge Signal Power Limitations
Title
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B
Appendix B: External Component Specifications
Table B-1 lists the transformer specifications. Table B-2 lists the REFCKI crystal oscillator specifications. Figure B-1 illustrates the minimum hardware configuration.
Table B-1. Transformer Specifications Parameter
Turns Ratio Pulse Engineering Part Number: Temp. 0 C to 70 C Octal SMT Serial Resistance Primary Inductance Isolation Voltage Leakage Inductance
RX Value
2:1 CT Pulse (1) T1124
TX Value
1:2
1 maximum OCL 1.2 mH @ 25 C 1500 Vrms 0.8 H
Note(s): (1) Contact Pulse Engineering for other part numbers: Phone (619) 674-8100 Web: http://www.pulseeng.com
Table B-2. REFCKI (10 MHz) Crystal Oscillator Specifications Parameter
Nominal Frequency Frequency Accuracy (E1) Frequency Accuracy (T1) Output Level (1) Aging 10 MHz 50 ppm 32 ppm 3.3 V Logic, CMOS or TTL 2 ppm/year, 10 ppm maximum
Value
Note(s): (1) If the VGG pin is connected to +5 V supply, 5 V logic output may be used. Refer to the VGG pin description in Chapter 1.0, Pin Descriptions .
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B
B-2 Advance Information
Appendix B: Applications
Figure B-1. Minimum Hardware Configuration
VDD Hardware Mode Host Mode 65 NC 48 43 NC NC 44 NC 45 NC 46 NC 114 NC 49 NC 62 NC 63 NC 64 NC 50 NC 47 NC 53 34 33 35 123 NC 119 NC 73 NC 42 NC 108 NC 115 NC 37 36 38 HM RESET JDIR(4) JSEL(2)(4) JSEL(1)(4) JSEL(0) UNIPOLAR HTERM PTS(2) PTS(1) PTS(0) CLK_POL IRQ ZCS RPOSO[1] RNEGO[1] RCKO[1] RLOOP[1] LLOOP[1] RAWMD[1] JATERR[1]* RLOS[1] TAIS[1] TPOSI[1] TNEGI[1] TCLK[1] XRING[1]
Channel 1 Line Interface Programmable Receive Termination (1) RTIP[1] 71 470 100 0.1 RRING[1] XOE[1] 72 470 1:2 66
RX
Fixed Receive Termination (2) RX
Channel 1 Digital Interface
RJ48C or BANTAM
TX
XTIP[1]
67 150 pF 68 Smoothing Capacitor Fixed Transmit Termination (3) 21
1:2
5.6(5) Optional Common Mode Choke 5.6
(5)
TX
Conexant
8380_026
CN8394 Quad T1/E1 Framer
Channel 2 Digital Interface
Octal Transformer Pulse - T1124
CN8380 Quad T1/E1 LIU
Channel 2 Line Interface
Channel 3 Line Interface
Channel 3 Digital Interface VDD VAA VAAT[1:4] VAAR VAACL VGG 42 44 43 45 1 NC 4 127 128 SDO(4) VSS SDI(4) Host Mode GND SCLK(4) Serial Port GNDT[1:4] (4) CS GNDR CLADI GNDCL REFCKI EACKI TACKI
Channel 4 Line Interface
Channel 4 Digital Interface
+3.3 V
10 MHz Oscillator
Quad T1/E1 Line Interface
Note(s): (1) Optional programmable receive termination: 75/100/120 (2) Required fixed receive termination. The parallel combination of the fixed termination and programmable termination must match the line impedance. (3) Optional fixed transmit termination. The value shown provides acceptable transmit return loss for T1 and E1 applications. (See Table 2-7, Transmit Termination Option D.) (4) Pins shown twice for Hardware Mode and Host Mode. (5) In Hardware Mode, 5.6 line feed resistors are required. In Host Mode, they are optional.
N8380DSA
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C
Appendix C: Acronym List
Acronym
AGC AIS AMI ANSI B8ZS BABT BPV BSDL CCIR CIF CLAD CMOS CRC CSU DAC DMA DPM DSX ETSI FCC FIFO GPIO HDB3 HDSL I2C ISDN ITU-T JAT JTAG LAL
Definition
automatic gain control alarm indication signal alternate mark inversion American National Standards Institute binary with 8-zero substitution British Approvals Board for Telecommunications bipolar violation boundary scan description language International Radio Communications Committee common interchange format clock rate adapter complementary metal-oxide semiconductor cyclic redundancy check channel service unit digital-to-analog converter direct memory access driver performance monitor digital signal cross connect European Telecommunications Standards Institute Federal Communications Commission first-in first-out buffer general purpose input/output high-density bipolar of order 3 high bit-rate digital subscriber line inter-integrated circuit Integrated Services Digital Network International Telegraph and Telephone Consultative Committee jitter attenuator Joint Test Action Group local analog loopback
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Appendix C : Acronym List
CN8380
Quad T1/E1 Line Interface
LDL LIU LOS MSB NCO NCTE NRZ PCI PCM PLL MQFP PRBS PRI RALOS RLL RLOS RPLL RZCS SDH SONET TAP TLOC TLOS TZCS UI UTP ZCS
local digital loopback line interface unit loss of signal most significant bit numerically controlled oscillator network channel-terminating equipment non-return to zero peripheral component interconnect pulse code modulation phase locked loop metric quad flat pack pseudo-random bit sequence primary rate interface receive loss of analog input remote line loopback receive loss of signal receive phase lock loop receive zero code suppression Synchronous Digital Hierarchy Synchronous Optical Network test access port transmit loss of clock transmit loss of signal transmit zero code suppression unit interval unshielded twisted pair zero code suppression
C-2
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N8380DSA 4/21/99
0.0 Sales Offices
Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com Hong Kong Phone: (852) 2827 0181 Fax: (852) 2827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 Phone: (82 53) 745 2880 Fax: (82 53) 745 1440
World Headquarters
Conexant Systems, Inc. 4311 Jamboree Road P. O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Mid-Atlantic Phone: (215) 244-6784 Fax: (215) 244-9292 U.S. North Central Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. Northeast Phone: (978) 692-7660 Fax: (978) 692-8185 U.S. Northwest/Pacific West Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. South Central Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Southeast Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southwest Phone: (949) 483-9119 Fax: (949) 483-9090
Europe Headquarters
Conexant Systems France Les Taissounieres B1 1681 Route des Dolines BP 283 06905 Sophia Antipolis Cedex FRANCE Phone: (33 4) 93 00 33 35 Fax: (33 4) 93 00 33 03 Europe Central Phone: (49 89) 829 1320 Fax: (49 89) 834 2734 Europe Mediterranean Phone: (39 02) 9317 9911 Fax: (39 02) 9317 9913 Europe North Phone: (44 1344) 486 444 Fax: (44 1344) 486 555 Europe South Phone: (33 1) 41 44 36 50 Fax: (33 1) 41 44 36 90
Middle East Headquarters
Conexant Systems Commercial (Israel) Ltd. P. O. Box 12660 Herzlia 46733, ISRAEL Phone: (972 9) 952 4064 Fax: (972 9) 951 3924
Japan Headquarters
Conexant Systems Japan Co., Ltd. Shimomoto Building 1-46-3 Hatsudai, Shibuya-ku, Tokyo 151-0061 JAPAN Phone: (81 3) 5371-1567 Fax: (81 3) 5371-1501
APAC Headquarters
Conexant Systems Singapore, Pte. Ltd. 1 Kim Seng Promenade Great World City #09-01 East Tower SINGAPORE 237994 Phone: (65) 737 7355 Fax: (65) 737 9077 Australia Phone: (61 2) 9869 4088 Fax: (61 2) 9869 4077 China Phone: (86 2) 6361 2515 Fax: (86 2) 6361 2516
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd. Room 2808 International Trade Building 333 Keelung Road, Section 1 Taipei 110, TAIWAN, ROC Phone: (886 2) 2720 0282 Fax: (886 2) 2757 6760

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